ST92F124R1 STMicroelectronics, ST92F124R1 Datasheet - Page 108
ST92F124R1
Manufacturer Part Number
ST92F124R1
Description
8/16-bit Single Voltage Flash Mcu Family With Ram, E?? Emulated Eeprom , Can 2.0b And J1850 Blpd
Manufacturer
STMicroelectronics
Datasheet
1.ST92F124R1.pdf
(429 pages)
- Current page: 108 of 429
- Download datasheet (8Mb)
ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
EXTERNAL INTERRUPT VECTOR REGISTER
(EIVR)
R246 - Read/Write
Register Page: 0
Reset value: xxxx 0110 (x6h)
Bits 7:4 = V[7:4]: Most significant nibble of Exter-
nal Interrupt Vector.
These bits are not initialized by reset. For a repre-
sentation of how the full vector is generated from
V[7:4] and the selected external interrupt channel,
refer to
Bit 3 = TLTEV: Top Level Trigger Event bit.
This bit is set and cleared by software.
0: Select falling edge as NMI trigger event
1: Select rising edge as NMI trigger event
Bit 2 = TLIS: Top Level Input Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is TL interrupt source
1: NMI is TL interrupt source
Bit 1 = IA0S: Interrupt Channel A0 Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is INTA0 source (the
1: External Interrupt pin is INTA0 source
Bit 0 = EWEN: External Wait Enable.
This bit is set and cleared by software.
108/429
9
V7
(the IA0S bit must be set in this case)
TLIS bit must be set in this case)
7
V6
Figure
V5
51.
V4 TLTEV TLIS IAOS EWEN
0
0: WAITN pin disabled
1: WAITN pin enabled (to stretch the external
Note: For more details on Wait mode refer to the
section describing the WAITN pin in the External
Memory Chapter.
NESTED INTERRUPT CONTROL (NICR)
R247 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
Bit 7 = TLNM: Top Level Not Maskable.
This bit is set by software and cleared only by a
hardware reset.
0: Top Level Interrupt Maskable. A top level re-
1: Top Level Interrupt Not Maskable. A top level
Bits 6:0 = HL[6:0]: Hold Level x
These bits are set by hardware when, in Nested
Mode, an interrupt service routine at level x is in-
terrupted from a request with higher priority (other
than the Top Level interrupt request). They are
cleared by hardware at the iret execution when
the routine at level x is recovered.
TLNM HL6
memory access cycle).
quest is generated if the IEN, TLI and TLIP bits
=1
request is generated if the TLIP bit =1
7
HL5
HL4
HL3
HL2
HL1
HL0
0
Related parts for ST92F124R1
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
STMicroelectronics [RIPPLE-CARRY BINARY COUNTER/DIVIDERS]
Manufacturer:
STMicroelectronics
Datasheet:
Part Number:
Description:
STMicroelectronics [LIQUID-CRYSTAL DISPLAY DRIVERS]
Manufacturer:
STMicroelectronics
Datasheet:
Part Number:
Description:
BOARD EVAL FOR MEMS SENSORS
Manufacturer:
STMicroelectronics
Datasheet:
Part Number:
Description:
NPN TRANSISTOR POWER MODULE
Manufacturer:
STMicroelectronics
Datasheet:
Part Number:
Description:
TURBOSWITCH ULTRA-FAST HIGH VOLTAGE DIODE
Manufacturer:
STMicroelectronics
Datasheet:
Part Number:
Description:
Manufacturer:
STMicroelectronics
Datasheet:
Part Number:
Description:
DIODE / SCR MODULE
Manufacturer:
STMicroelectronics
Datasheet:
Part Number:
Description:
DIODE / SCR MODULE
Manufacturer:
STMicroelectronics
Datasheet:
Part Number:
Description:
Search -----> STE16N100
Manufacturer:
STMicroelectronics
Datasheet:
Part Number:
Description:
Search ---> STE53NA50
Manufacturer:
STMicroelectronics
Datasheet:
Part Number:
Description:
NPN Transistor Power Module
Manufacturer:
STMicroelectronics
Datasheet:
Part Number:
Description:
DIODE / SCR MODULE
Manufacturer:
STMicroelectronics
Datasheet: