ADN2804 Analog Devices, Inc., ADN2804 Datasheet
ADN2804
Related parts for ADN2804
ADN2804 Summary of contents
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... The receiver’s front-end loss-of-signal (LOS) detector circuit indicates when the input signal level falls below a user-adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2804 is available in a compact 5 mm × 5 mm, 32-lead LFCSP. FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN ...
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... ADN2804 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Jitter Specifications....................................................................... 4 Output and Timing Specifications ............................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Timing Characteristics..................................................................... 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. Interface Timing and Internal Register Description........... 10 Terminology ...
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... PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity. 2 When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the ADN2804 input stage. = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2 F ...
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... Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer Bandwidth Jitter Peaking Jitter Generation Jitter Tolerance 1 Jitter tolerance of the ADN2804 at these jitter frequencies is better than what the test equipment is able to measure. , VEE = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2 F Conditions OC-12 OC-12 OC-12, 12 kHz to 5 MHz ...
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... 2 2 0.4 V − −2 Rev Page ADN2804 Typ Max Unit 1475 mV mV 320 400 mV 1200 1275 mV 100 Ω 115 220 ps 115 220 ps 800 840 ps 800 840 ps V 0.3 VCC V +10.0 μA ...
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... ADN2804 ABSOLUTE MAXIMUM RATINGS VCC = MIN MAX MIN MAX 0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Range ESD CAUTION ESD (electrostatic discharge) sensitive device ...
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... TIMING CHARACTERISTICS CLKOUTP DATAOUTP/ DATAOUTN Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP Figure 3. Differential Output Specifications 5mA R LOAD 100Ω 100Ω 5mA SIMPLIFIED LVDS OUTPUT STAGE Figure 4. Differential Output Stage Rev Page DIFF ADN2804 ...
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... Exposed Pad Pad 1 Type power analog input analog output digital input digital output. TEST1 1 PIN 1 INDIC ATOR VCC 2 VREF 3 ADN2804* NIN 4 PIN 5 TOP VIEW (Not to Scale) SLICEP 6 SLICEN 7 VEE 8 * THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND. ...
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... TYPICAL PERFORMANCE CHARACTERISTICS 100 1k Figure 6. LOS Comparator Trip Point Programming Rev Page 10k 100k ADN2804 ...
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... ADN2804 INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION S SLAVE ADDR, LSB = 0 (WR) A(S) S SLAVE ADDR, LSB = 0 (WR START BIT A(S) = ACKNOWLEDGE BY SLAVE START BIT SLAVE ADDRESS SDA A6 A5 SCK S SLADDR[4... SDA t SCK S SLAVE ADDRESS [6... MSB = 1 SET BY PIN 19 Figure 7. Slave Address Configuration ...
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... System Reset D5 D4 Write a 1 followed by Set reset ADN2804 Config LOS SQUELCH Mode Set Active high LOS 0 = Squelch data outputs and clock outputs 1 = Active low LOS 1 = Squelch data outputs or clock outputs Rev Page ...
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... Single-Ended vs. Differential AC coupling is typically used to drive the inputs to the quantizer. The inputs are internally dc biased to a common- mode potential of ~2.5 V. Driving the ADN2804 in a single- ended fashion and observing the quantizer input with an oscilloscope probe at the point indicated in Figure 13 shows a binary signal with an average value equal to the common-mode potential and instantaneous values both above and below the average value ...
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... JITTER SPECIFICATIONS The ADN2804 CDR is designed to achieve the best bit- error-rate (BER) performance and to exceed the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia Technologies specification. Jitter is the dynamic displacement of digital signal edges from their long-term average positions, measured in unit intervals (UI), where bit period ...
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... ADN2804 THEORY OF OPERATION The ADN2804 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops, which share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter ...
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... The jitter accommodation is roughly 0 this region. The corner frequency between the declining slope and the flat region is the closed-loop bandwidth of the delay-locked loop, which is roughly 1.0 MHz at 622 Mbps. Rev Page ADN2804 ...
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... Figure 19. LOS Detector Hysteresis The LOS detector and the SLICE level adjust can be used simultaneously on the ADN2804. This means that any offset added to the input signal by the SLICE adjust pins does not affect the LOS detector’s measurement of the absolute input level. ...
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... The lock detector on the ADN2804 has three modes of operation: normal mode, REFCLK mode, and static LOL mode. Normal Mode In normal mode, the ADN2804 is a CDR that locks onto a 622 Mbps data rate without the use of a reference clock as an acquisition aid. In this mode, the lock detector monitors the ...
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... Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADN2804 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADN2804 has eight subaddresses to enable the user-accessible internal registers (see Table 6 through Table 10) ...
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... MHz, and CTRLA[5:2] is set to [0101], that is, 5, because 622.08 Mbps/19.44 MHz = 2 In this mode, if the ADN2804 loses lock for any reason, it relocks onto the reference clock and continues to output a stable clock. While the ADN2804 is operating in lock-to-reference mode, ...
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... The accuracy error of the reference clock is added to the accuracy of the ADN2804 data rate measurement. For example 100 ppm accuracy reference clock is used, the total accuracy of the measure- ment is within 200 ppm. ...
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... Use μF electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they should be placed between ADN2804 supply pins VCC and VEE, as close as possible to the ADN2804 VCC pins. VCC + 22µ ...
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... UI p-p typical the rise time, which is equal to 0.22/BW, r where BW ~ 0.7 (bit rate). Note that this expression for t The output rise time for the ADN2804 is ~100 ps regardless of the data rate. Rev Page −t/τ ); therefore, τ = 12t (−nT/RC − e )/0 ...
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... EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER DOES NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2804. THE QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT. ...
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... ADN2804ACPZ-500RL7 −40°C to +85°C 1 ADN2804ACPZ-RL7 −40°C to +85°C EVAL-ADN2804EB Pb-free part. 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © ...