ADN2811 Analog Devices, Inc., ADN2811 Datasheet
ADN2811
Related parts for ADN2811
ADN2811 Summary of contents
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... The receiver front end signal detect circuit indicates when the input signal level has fallen below a user-adjustable threshold. The signal detect circuit has hysteresis to prevent chatter at the output. The ADN2811 is available in a compact × 7 mm, 48-lead chip scale package. FUNCTIONAL BLOCK DIAGRAM VEE ...
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... ADN2811 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics .............................................................. 5 ESD Caution.................................................................................. 5 Pin Configuration and Functional Descriptions.......................... 6 Definition of Terms .......................................................................... 8 Maximum, Minimum, and Typical Specifications ................... 8 Input Sensitivity and Input Overdrive....................................... 8 Single-Ended vs. Differential ...................................................... 8 LOS Response Time ..................................................................... 9 Jitter Specifications....................................................................... 9 Theory of Operation ...................................................................... 10 Functional Description .................................................................. 12 Clock and Data Recovery .......................................................... 12 REVISION HISTORY 5/04— ...
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... PIN–NIN = 10 mV p-p OC-48 OC-48 OC-48, 12 kHz–20 MHz OC-48 (See Figure 11) 600 Hz 6 kHz 100 kHz 1 MHz V (See Figure (See Figure 5) DIFF 20% to 80% 80% to 20% Rev Page ADN2811 Min Typ Max 0 1.2 2.4 0.4 − 500 244 1.9 54 −15 100 0.65 10 0.115 0.200 0.300 − ...
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... ADN2811 Parameter Setup Time Hold Time REFCLK DC INPUT CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Common-Mode Level TEST DATA DC INPUT CHARACTERISTICS Peak-to-Peak Differential Input Voltage LVTTL DC INPUT CHARACTERISTICS Input High Voltage Input Low Voltage Input Current LVTTL DC OUTPUT CHARACTERISTICS ...
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... Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. THERMAL CHARACTERISTICS Ratings Thermal Resistance 5.5 V 48-lead LFCSP, 4-layer board with exposed paddle soldered VEE − 0 VCC VCC + 0.4 V 165°C θ = 25°C/W JA −65°C to +150°C 300°C Rev Page ADN2811 ...
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... SDOUT DO 48 LOOPEN DI 1 Type Power Analog Input Analog Output Digital Input Digital Output THRADJ 1 PIN 1 VCC 2 INDICATOR VEE 3 VREF 4 PIN 5 ADN2811 NIN 6 SLICEP 7 TOPVIEW SLICEN 8 VEE 9 LOL 10 XO1 11 XO2 12 Figure 2. Pin Configuration 1 Description LOS Threshold Setting Resistor. Analog Supply. Ground. ...
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... THRADJ RESISTOR VS. LOS TRIP POINT Figure 4. LOS Comparator Trip Point Programming OUTP V CML OUTN OUTP–OUTN DIFF 0V Figure 5. Single-Ended vs. Differential Output Specs 100 RESISTANCE (kΩ) Rev Page ADN2811 V SE ...
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... SINGLE-ENDED VS. DIFFERENTIAL AC-coupling is typically used to drive the inputs to the quantizer. The inputs are internally dc biased to a common- mode potential of ~0.6 V. Driving the ADN2811 single-ended and observing the quantizer input with an oscilloscope probe at the point indicated in Figure 7 shows a binary signal with an average value equal to the common-mode potential and instantaneous values both above and below the average value ...
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... The LOS response time is the delay between the removal of the input signal and the indication of loss of signal (LOS) at SDOUT. The LOS response time of the ADN2811 is 300 ns typ when the inputs are dc-coupled. In practice, the time constant of the ac-coupling at the quantizer input determines the LOS response time ...
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... ADN2811 THEORY OF OPERATION The ADN2811 is a delay-locked and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of the input jitter ...
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... UI in this region. The corner frequency between the declining slope and the flat region is the closed-loop bandwidth of the delay-locked loop, which is roughly 5 MHz. JITTER GAIN (dB) n psh Figure 13. Jitter Response vs. Conventional PLL Rev Page ADN2811 JITTER PEAKING IN ORDINARY PLL ADN2811 Z(s) X(s) f (kHz) d psh o c ...
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... ADN2811 FUNCTIONAL DESCRIPTION CLOCK AND DATA RECOVERY The ADN2811 recovers clock and data from serial bit streams at OC-48 as well as the 15/14 FEC rates. The data rate is selected by the RATE input (see Table 4). Table 4. Data Rate Selection RATE Data Rate Frequency (MHz) 0 OC-48 2488.32 ...
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... The ADN2811 can accept any of the following reference clock frequencies: 19.44 MHz, 38.88 MHz, 77.76 MHz at LVTTL/ LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/ LVDS levels via the REFCLKN/P inputs, independent of data rate. The input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mV (e ...
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... CML outputs. Bypass and loopback modes are mutually exclusive. Only one of these modes can be used at any given time. The ADN2811 is put into an indeterminate state if the BYPASS and LOOPEN pins are set to Logic 1 at the same time. Rev Page ...
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... PCB. 0.1 µF and 1 nF ceramic chip capacitors should be placed between IC power supply VCC and GND as close as possible to the ADN2811’s VCC pins. Again, if connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance, especially on Pins 35 and 36, which supply power to the high speed CLKOUTP/N and DATAOUTP/N output buffers ...
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... VEE 34 VEE RATE µC 30 VEE 29 VCC 28 0.1µF VEE 1nF 27 VCC 26 CF2 25 4.7µF (SEE TABLE 7 FOR SPECS) VCC 0.1µF VCC ADN2811 C 50Ω IN PIN TIA C 50Ω IN NIN 50Ω VREF 0.1µ F Figure 21. AC-Coupled Input Configuration VCC VCC 50Ω ...
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... THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2811. THE QUANTIZER WILL BE ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT. ...
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... Logic 0 while the frequency loop and phase loop swap control of the VCO. The chain of events is as follows: • The ADN2811 is locked to the input data stream; LOL = 0. • The input data stream is lost due to a break in the link. The VCO frequency drifts until the frequency error is greater than 1000 ppm ...
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... Figure 26. 48-Lead Frame Chip Scale Package [LFCSP × Body (CP-48) Dimensions shown in millimeters Package Description 48-Lead LFCSP 48-Lead LFCSP, Tape-Reel, 2500 pcs Evaluation Board Rev Page 0.30 0.23 0.60 MAX 0.18 PIN 1 INDICATOR 48 1 EXPOSED 5.25 PAD 5.10 SQ (BOTTOM VIEW) 4. 0.25 MIN 5.50 REF Package Option CP-48 CP-48 ADN2811 ...
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... ADN2811 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03019–0–5/04(B) Rev Page ...