ADN2815 Analog Devices, Inc., ADN2815 Datasheet
ADN2815
Related parts for ADN2815
ADN2815 Summary of contents
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... All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. The ADN2815 is available in a compact 5 mm × 32-lead LFCSP. FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN ...
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... ADN2815 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Jitter Specifications....................................................................... 4 Output and Timing Specifications ............................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Timing Characteristics..................................................................... 7 Pin Configuration and Function Descriptions............................. Interface Timing and Internal Register Description............. 9 Jitter Specifications ...
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... PIN or NIN, dc-coupled PIN − NIN DC-coupled @ 2.5 GHz Differential With respect to nominal With respect to nominal 10 Mb/s OC-12 GbE GbE OC-12 OC-3 OC-1 10 Mb/s See Table 13 In addition to REFCLK accuracy Data rate ≤ 20 Mb/s Data rate > 20 Mb/s Locked to 1.25 Gb/s Rev Page ADN2815 23 − 1, Min Typ Max Unit 1.8 2.8 V 0.2 2.0 V 2.3 2.5 2 1250 Mb/s −15 ...
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... Table 2. Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW Jitter Peaking Jitter Generation Jitter Tolerance 1 Jitter tolerance of the ADN2815 at these jitter frequencies is better than what the test equipment is able to measure. , VEE = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2 F Conditions OC-12 OC-3 OC-12 OC-3 OC-12, 12 kHz to 5 MHz OC-3, 12 kHz to 1 ...
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... 2 2 0.4 V − −2 Rev Page ADN2815 Typ Max Unit 1475 mV mV 320 400 mV 300 400 mV 1200 1275 mV 100 Ω 115 220 ps 115 220 ps 400 440 ps 400 440 ps V 0.3 VCC V +10 ...
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... ADN2815 ABSOLUTE MAXIMUM RATINGS VCC = MIN MAX MIN MAX 0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Range ESD CAUTION ESD (electrostatic discharge) sensitive device ...
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... TIMING CHARACTERISTICS CLKOUTP DATAOUTP/ DATAOUTN Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP Figure 3. Differential Output Specifications 5mA R LOAD V 100Ω 100Ω 5mA SIMPLIFIED LVDS OUTPUT STAGE Figure 4. Differential Output Stage Rev Page ADN2815 DIFF ...
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... TEST2 Exposed Pad Pad 1 Type power analog input analog output digital input digital output. TEST1 1 PIN 1 INDICATOR VCC 2 VREF 3 ADN2815* NIN 4 PIN 5 TOP VIEW (Not to Scale VEE 8 * THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND. ...
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... C Data Transfer Timing t SU;DAT HIGH t SU;STA S t HD;DAT 2 Figure 10 Port Timing Diagram Rev Page R/W CTRL A(S) DATA A(S) P A(S) DATA A(M) DATA A(M) A(M) = LACK OF ACKNOWLEDGE BY MASTER DATA D7 D0 ACK ACK DATA[6...1] t HD;STA t BUF SU;STO P S ADN2815 P STOP BIT P ...
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... System Reset D5 D4 Write a 1 followed by Set reset ADN2815 SQUELCH Mode Set to 0 Set SQUELCH CLK and DATA 1 = SQUELCH CLK or DATA Rev Page LSB LSB LSB COARSE_RD[1] Data Rate ...
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... JITTER SPECIFICATIONS The ADN2815 CDR is designed to achieve the best bit-error- rate (BER) performance and exceeds the jitter transfer, genera- tion, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia Technologies specification. Jitter is the dynamic displacement of digital signal edges from their long-term average positions, measured in unit intervals (UI), where bit period ...
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... ADN2815 THEORY OF OPERATION The ADN2815 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter ...
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... The jitter accommodation is roughly 0 this region. The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 1.5 MHz at 1.25 Gb/s. Rev Page ADN2815 ...
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... Static LOL Mode The ADN2815 implements a static LOL feature, which indicates if a loss-of-lock condition has ever occurred and remains asserted, even if the ADN2815 regains lock, until the static LOL bit is manually reset. The I LOL bit. If there is ever an occurrence of a loss-of-lock condition, this bit is internally asserted to logic high ...
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... Logic 1 on the LSB of the first byte means that = 1/155.52 MHz. the master reads information from the peripheral. The ADN2815 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses, plus the R/W bit. The ADN2815 has eight subaddresses to enable the user-accessible internal registers (see Table 6 through Table 10) ...
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... Data Rate/2 The user must know exactly what the data rate is and provide a reference clock that is a function of this rate. The ADN2815 can still be used as a continuous rate device in this configuration, provided that the user has the ability to provide a reference clock that has a variable frequency (see Application Note AN-632) ...
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... MHz. CTRLA[5:2] is set to [0101], that is, 5, because 5 622.08 Mb/s/19.44 MHz = 2 In this mode, if the ADN2815 loses lock for any reason, it relocks onto the reference clock and continues to output a stable clock. While the ADN2815 is operating in lock-to-reference mode, if the user ever changes the reference frequency, the F ...
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... System Reset A frequency acquisition can be initiated by writing a 1 followed 2 C interface the I frequency acquisition while keeping the ADN2815 in the operating mode that it was previously programmed to in Registers CTRL[A], CTRL[B], and CTRL[C]. Rev Page Register Bit CTRLB[5]. This initiates a new ...
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... Use μF electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they should be placed between the IC power supply VCC and VEE, as close as possible to the ADN2815 VCC pins. VCC + 22μF 0.1μ ...
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... UI p-p typical the rise time, which is equal to 0.22/BW, r where BW ~ 0.7 (bit rate). Note that this expression for t The output rise time for the ADN2815 is ~100 ps, regardless of data rate. Rev Page –t/τ ); therefore, τ = 12t ( ) ( ) − ...
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... EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER DOES NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2815. THE QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT. ...
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... ADN2815 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 13. Look-Up Table Code F Code MID 0 5.3745e+ 5.3741e+ 5.4793e+ 5.5912e+ 5.7111e+ 5.8391e+ 5.9760e+ 6.1215e+ 6.2780e+ 6.4565e+ ...
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... Rev Page ADN2815 Code F MID 240 9.8129e+08 241 9.8124e+08 242 1.0012e+09 243 1.0225e+09 244 1.0453e+09 245 1.0697e+09 246 1.0959e+09 247 1.1239e+09 248 1 ...
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... ADN2815ACPZ-500RL7 −40°C to 85°C 1 ADN2815ACPZ-RL7 −40°C to 85°C EVAL-ADN2815EB Pb-free part. Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Patent Rights to use these components © ...