ADN2819 Analog Devices, Inc., ADN2819 Datasheet
ADN2819
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ADN2819 Summary of contents
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... The receiver front end signal detect circuit indicates when the input signal level has fallen below a user-adjustable threshold. The signal detect circuit has hysteresis to prevent chatter at the output. The ADN2819 is available in a compact 7 mm × 7 mm, 48-lead chip scale package. FUNCTIONAL BLOCK DIAGRAM VEE ...
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... ADN2819 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Definition of Terms.......................................................................... 9 Maximum, Minimum, and Typical Specifications ................... 9 Input Sensitivity and Input Overdrive....................................... 9 Single-Ended vs. Differential ...................................................... 9 LOS Response Time ................................................................... 10 Jitter Specifications..................................................................... 10 Theory of Operation ...................................................................... 12 Functional Description .................................................................. 14 Multirate Clock and Data Recovery......................................... 14 REVISION HISTORY 5/04— ...
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... OC-48, PRBS kΩ THRESH kΩ THRESH kΩ THRESH 7 OC-12, PRBS kΩ THRESH kΩ THRESH kΩ THRESH Rev Page ADN2819 Min Typ Max Unit 0 1.2 V 2.4 V 0.4 V – p p-p 500 µV 244 µV rms 1 ...
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... ADN2819 Parameter Hysteresis (Electrical) (continued) LOSS OF LOCK DETECTOR (LOL) Loss of Lock Response Time POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW Jitter Peaking Jitter Generation Jitter Tolerance CML OUTPUTS (CLKOUTP/N, DATAOUTP/N) Single-Ended Output Swing Differential Output Swing Output High Voltage ...
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... DC-coupled, single-ended 4 (TDINP/N) CML inputs –2 +2 Rev Page ADN2819 Min Typ Max Unit 140 ps 350 ps 750 ps 3145 ps 150 ps 350 ps 750 ps 3150 ps 0 VCC V 100 mV VCC/2 V 0.8 V 2.0 V ...
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... ADN2819 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Lead Temperature (Soldering 10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...
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... Differential Recovered Clock Output. CML. Bypass CDR Mode. Active high. LVTTL. Loss of Signal Detect Output. Active high. LVTTL. Enable Test Data Inputs. Active high. LVTTL. Rev Page VCC 35 VCC 34 VEE 33 VEE 32 SEL0 31 SEL1 30 SEL2 29 VEE 28 VCC 27 VEE 26 VCC 25 CF2 ADN2819 ...
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... ADN2819 CLKOUTP DATAOUTP HYSTERESIS (dB) Figure 5. LOS Hysteresis OC-3, –40°C, 3 – 1 PRBS Input Pattern, R OUTP V CML OUTN OUTP–OUTN Figure 3. Output Timing 18 THRADJ RESISTOR VS. LOS TRIP POINT ...
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... SINGLE-ENDED VS. DIFFERENTIAL AC-coupling is typically used to drive the inputs to the quantizer. The inputs are internally dc biased to a common- mode potential of ~0.6 V. Driving the ADN2819 single-ended and observing the quantizer input with an oscilloscope probe at the point indicated in Figure 9 shows a binary signal with an average value equal to the common-mode potential and instantaneous values above and below the average value ...
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... The LOS response time is the delay between the removal of the input signal and indication of loss of signal (LOS) at SDOUT. The ADN2819’s response time is 300 ns typ when the inputs are dc-coupled. In practice, the time constant of ac-coupling at the quantizer input determines the LOS response time. ...
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... Table 4. Jitter Transfer and Tolerance: SONET Spec vs. ADN2819 Jitter Transfer ADN2819 Rate SONET Spec (f ) (kHz) C OC-48 2 MHz 590 OC-12 500 kHz 140 OC-3 130 kHz 48 1 Jitter tolerance measurements limited by test equipment capabilities. ...
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... ADN2819 THEORY OF OPERATION The ADN2819 is a delay-locked and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of the input jitter ...
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... MHz for OC-12, OC-48, and GbE data rates, and 600 kHz for OC-3 data rates. JITTER GAIN (dB) n psh Figure 16. Jitter Response vs. Conventional PLL Rev Page ADN2819 JITTER PEAKING IN ORDINARY PLL ADN2819 Z(s) X(s) f (kHz) d psh o c ...
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... ADN2819 FUNCTIONAL DESCRIPTION MULTIRATE CLOCK AND DATA RECOVERY The ADN2819 will recover clock and data from serial bit streams at OC-3, OC-12, OC-48, and GbE data rates as well as the 15/14 FEC rates. The output of the 2.5 GHz VCO is divided down in order to support the lower data rates. The data rate is selected by the SEL[2 ...
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... OSCILLATOR XO2 REFSEL Figure 19. Crystal Oscillator Configuration The ADN2819 can accept any of the following reference clock frequencies: 19.44 MHz, 38.88 MHz, and 77.76 MHz at LVTTL/ LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/ LVDS levels via the REFCLKN/P inputs, independent of data rate (including Gigabit Ethernet and wrapper rates). The input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mV (e ...
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... CML outputs. Bypass and loopback modes are mutually exclusive: only one of these modes can be used at any given time. The ADN2819 is put into an indeterminate state if both the BYPASS and LOOPEN pins are set to Logic 1 at the same time. ...
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... PCB. Use of 0.1 µF and 1 nF ceramic chip capacitors should be placed between IC power supply VCC and GND as close as possible to the ADN2819 VCC pins. Again, if connections to the supply and ground are made through vias, the use of multiple vias in parallel will help to reduce series inductance, especially on Pins 35 and 36, which supply power to the high speed CLKOUTP/N and DATAOUTP/N output buffers ...
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... VEE 34 VEE 33 SEL0 32 SEL1 µC 31 SEL2 30 VEE 29 VCC 28 0.1µF VEE 1nF 27 VCC 26 CF2 25 4.7µF (SEE TABLE 8 FOR SPECS) VCC 0.1µF VCC ADN2819 C 50Ω IN PIN TIA C 50Ω IN NIN 50Ω VREF 0.1µ F Figure 24. AC-Coupled Input Configuration VCC VCC 50Ω ...
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... THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2819. THE QUANTIZER WILL BE ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT. ...
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... Logic 0, while the frequency loop and phase loop swap control of the VCO. The chain of events is as follows: • The ADN2819 is locked to the input data stream; LOL = 0. • The input data stream is lost due to a break in the link. The VCO frequency drifts until the frequency error is greater than 1000 ppm ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model ADN2819ACP-CML ADN2819ACP-CML-RL 1 ADN2819ACPZ-CML 1 ADN2819ACPZ-CML-RL EVAL-ADN2819-CML Free. 7.00 BSC SQ 0.60 MAX 36 TOP 6.75 VIEW BSC SQ 0.50 0.40 25 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 29. 48-Lead Lead Frame Chip Scale Package [LFCSP × ...
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... ADN2819 NOTES Rev Page ...
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... NOTES Rev Page ADN2819 ...
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... ADN2819 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02999–0–5/04(B) Rev Page ...