ADN2891 Analog Devices, Inc., ADN2891 Datasheet

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ADN2891

Manufacturer Part Number
ADN2891
Description
3.3 V, 3.2 Gbps, Limiting Amplifier
Manufacturer
Analog Devices, Inc.
Datasheet

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FEATURES
Input sensitivity: 4 mV p-p
80 ps rise/fall times
CML outputs: 700 mV p-p differential
Programmable LOS detector: 3.5 mV to 35 mV
Rx signal strength indicator (RSSI)
Single-supply operation: 3.3 V
Low power dissipation: 145 mW
Available in space-saving 3 mm × 3 mm, 16-lead LFCSP
Extended temperature range: −40°C to +95°C
SFP reference design available
APPLICATIONS
SFP/SFF/GBIC optical transceivers
OC-3/OC-12/OC-48, GbE, Fibre Channel (FC) receivers
10GBASE-LX4 transceivers
WDM transponders
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
SFF-8472-compliant average power measurement
ADN2880
PD_CATHODE
PD_VCC
PIN
NIN
FUNCTIONAL BLOCK DIAGRAM
CAZ1
50Ω
ADN2891
AVCC
0.01
50Ω
μ
3kΩ
AVEE
F
Figure 1.
CAZ2
V
REF
DETECTOR
RSSI/LOS
DRVCC
GENERAL DESCRIPTION
The ADN2891 is a 3.2 Gbps limiting amplifier with integrated
loss-of-signal (LOS) detection circuitry and a received signal
strength indicator (RSSI). This part is optimized for SONET,
Gigabit Ethernet (GbE), and Fibre Channel optoelectronic
conversion applications. The ADN2891 has a differential input
sensitivity of 4 mV p-p and accepts up to a 2.0 V p-p differential
input overload voltage. The ADN2891 supports current mode
logic (CML) outputs with controlled rise and fall times.
By monitoring the bias current through a photodiode, the on-
chip RSSI detector measures the average power received with
2% typical linearity over the entire valid input range of the
photodiode. The on-chip RSSI detector facilitates SFF-8472-
compliant optical transceivers by eliminating the need for
external RSSI detector circuitry.
Additional features include a programmable loss-of-signal
(LOS) detector and output squelch.
The ADN2891 is available in a 3 mm × 3 mm, 16-lead LFCSP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
DRVCC
THRADJ
50Ω
DRVEE
SQUELCH
50Ω
LOS
RSSI_OUT
©2005 Analog Devices, Inc. All rights reserved.
OUTP
OUTN
+V
Limiting Amplifier
10k
Ω
3.3 V, 3.2 Gbps,
ADuC7020
ADN2891
www.analog.com

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ADN2891 Summary of contents

Page 1

... The on-chip RSSI detector facilitates SFF-8472- compliant optical transceivers by eliminating the need for external RSSI detector circuitry. Additional features include a programmable loss-of-signal (LOS) detector and output squelch. The ADN2891 is available × 3 mm, 16-lead LFCSP. FUNCTIONAL BLOCK DIAGRAM AVCC AVEE DRVCC ...

Page 2

... ADN2891 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 Limiting Amplifier ..................................................................... 10 REVISION HISTORY 7/05—Rev Rev. A Changes to Table 1............................................................................ 3 Changes to Ordering Guide .......................................................... 13 3/05—Revision 0: Initial Version Loss of Signal (LOS) Detector .................................................. 10 Received Signal Strength Indicator (RSSI) ...

Page 3

... Measured at PD_CATHODE, with μ 3.3 3 +25 +95 °C T MIN 50 Ω Single-ended 660 850 mV p-p Differential 80 130 ps 20% to 80% Rev Page ADN2891 23 −10 − 1, BER ≤ − − 100 kΩ kΩ 23 − − 1 ≤ 1000 μ MAX ...

Page 4

... ADN2891 Parameter Min LOGIC INPUTS (SQUELCH Input High Voltage 2 Input Low Voltage IL Input Current LOGIC OUTPUTS (LOS Output High Voltage 2 Output Low Voltage OL Typ Max Unit Test Conditions/Comments V 0 μA I INH 6 μA I INL V Open drain output, 4.7 kΩ kΩ ...

Page 5

... THERMAL RESISTANCE J-STD-20 θ is specified for 4-layer PCB with exposed paddle soldered JA 125°C to GND. Table 3. Package Type 3 mm × 3 mm, 16-lead LFCSP Rev Page ADN2891 θ Unit JA 28 °C/W ...

Page 6

... PD_VCC P 16 PD_CATHODE AO Exposed Pad P Pad power digital input digital output analog input; and AO = analog output AVCC DRVCC 1 12 ADN2891 PIN OUTP 2 11 TOP VIEW NIN OUTN 3 10 (Not to Scale) AVEE DRVEE Figure 2. Pin Configuration ...

Page 7

... Figure 4. Eye of ADN2891 @ 25°C, 3.2 Gbps, and 500 mV Input 50ps/DIV Figure 5. Eye of ADN2891 @ 95°C, 3.2 Gbps, and 10 mV Input Figure 6. Eye of ADN2891 @ 95°C, 3.2 Gbps, and 500 mV Input Figure 7. Eye of ADN2891 @ 25°C, 155 Mbps, and 10 mV Input Rev Page ADN2891 50ps/DIV 1ns/DIV ...

Page 8

... ADN2891 70 60 –40°C 50 +95°C +25°C 40 +95°C 30 +25°C DEASSERTION 20 –40°C 10 ASSERTION 0 1k 10k R (Ω) TH Figure 8. LOS Trip and Release vs 10k R (Ω) TH Figure 9. LOS Electrical Hysteresis vs 6.0 6.3 6.6 6.9 7.2 7.5 7.8 ELECTRICAL HYSTERESIS (dB) Figure 10. Sample Lot Distribution— ...

Page 9

... TEMPERATURE (°C) Output and PD_CATHODE (Input) Current of 5 μA +100°C +30°C 200 400 600 800 PD_CATHODE CURRENT (μA) Figure 18. RSSI Linearity % vs. PD_CATHODE Current –40 – TEMPERATURE (°C) Figure 19. ADN2891 I Current vs. Temperature CC 80 100 –40°C 1000 100 120 ...

Page 10

... Additionally, TIA output offset drifts may degrade receiver performance. The ADN2891 limiting amplifier is a high gain device susceptible to dc offsets in the signal path. The pulse width distortion presented in the NRZ data or a distortion generated by the TIA may appear as dc offset or a corrupted signal to the ADN2891 inputs ...

Page 11

... C1–C4, C11: 0.01μF X5R/X7R DIELECTRIC, 0201 CASE C5, C7, C9, C10, C12: 0.1μF X5R/X7R DIELECTRIC, 0402 CASE C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE C11 R3 4.7kΩ TO 10kΩ C12 R2 ON HOST BOARD VCC Rev Page RSSI MEASUREMENT TO ADC C10 VCC HOST BOARD C4 ADN2891 ...

Page 12

... ADN2891 PCB Layout Figure 21 shows the recommended PCB layout. The 50 Ω transmission lines are the traces that bring the high frequency input and output signals (PIN, NIN, OUTP, and OUTN) to the SMA connectors with minimum reflection. To avoid a signal skew between the differential traces, each differential PIN/NIN and OUTP/OUTN pair should have matched trace lengths from the signal pins to the corresponding SMA connectors ...

Page 13

... Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters Package Description 16-Lead VQ_LFCSP, 500 pieces 16-Lead VQ_LFCSP, 1,500 pieces 16-Lead VQ_LFCSP, 5,000 pieces Evaluation Board Rev Page 0.50 0.40 0. 1.35 EXPOSED PAD 9 (BOTTOM VIEW 0.25 MIN Package Option CP-16-3 CP-16-3 CP-16-3 ADN2891 Branding F04 F04 F04 ...

Page 14

... ADN2891 NOTES Rev Page ...

Page 15

... NOTES Rev Page ADN2891 ...

Page 16

... ADN2891 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05244–0–7/05(A) Rev Page ...

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