ADRF6601 Analog Devices, Inc., ADRF6601 Datasheet - Page 15

• Manufacturer Part Number: ADRF6601
• Description: 750 Mhz To 1160 Mhz Rx Mixer With Integrated Fractional-n Pll And Vco
• Manufacturer: Analog Devices, Inc.

THEORY OF OPERATION
The ADRF6601 integrates a high performance downconverting
mixer with a state-of-the-art fractional-N PLL. The PLL also inte-
grates a low noise VCO. The SPI port allows the user to control the
fractional-N PLL functions and the mixer optimization functions,
as well as allowing for an externally applied LO or VCO.
The mixer core within the ADRF6601 is the next generation of
an industry leading family of mixers from Analog Devices, Inc.
The RF input is converted to a current and then mixed down to
IF using high performance NPN transistors. The mixer output
currents are transformed to a differential output voltage.
The high performance active mixer core results in an excep-
tional IIP3 and IP1dB, with a very low output noise floor for
excellent dynamic range. Over the specified frequency range,
the ADRF6601 typically provides an IF input P1dB of 14.3 dBm
and an IIP3 of 31 dBm.
Improved performance at specific frequencies can be achieved
with the use of the internal capacitor DAC (CDAC), which is
programmable via the SPI port, and through the use of a resistor
to a 5 V supply from the IP3SET pin (Pin 29). Adjustment of
the capacitor DAC allows increments in phase shift at internal
nodes in the ADRF6601, thus allowing cancellation of third-
order distortion with no change in supply current. Connecting
a resistor to a 5 V supply from the IP3SET pin increases the
internal mixer core current, thereby improving overall IIP2 and
IIP3, as well as IP1dB. Using the IP3SET pin for this purpose
increases the overall supply current.
The fractional divide function of the PLL allows the frequency
multiplication value from REF_IN to LO output to be a frac-
tional value rather than be restricted to an integer value as
in traditional PLLs. In operation, this multiplication value is
where:
INT is the integer value.
FRAC is the fractional value.
MOD is the modulus value.
The INT, FRAC, and MOD values are all programmable via
the SPI port.
In other fractional-N PLL designs, fractional multiplication
is achieved by periodically changing the fractional value in a
deterministic way. The disadvantage of this approach is often
spurious components close to the fundamental signal. In the
ADRF6601, a Σ-Δ modulator is used to distribute the fractional
value randomly, thus significantly reducing the spurious content
due to the fractional function.
INT + ( FRAC / MOD )
Rev. 0 | Page 15 of 24
PROGRAMMING THE ADRF6601
The ADRF6601 is programmed via a 3-pin SPI port. The timing
requirements for the SPI port are shown in Figure 2. Eight pro-
grammable registers, each with 24 bits, control the operation of
the device. The register functions are listed in Table 8.
Table 8. ADRF6601 Register Functions
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Note that internal calibration for the PLL must be run when the
ADRF6601 is initialized at a given frequency. This calibration is
run automatically whenever Register 0, Register 1, or Register 2 is
programmed. Because the other registers affect PLL performance,
Register 0, Register 1, and Register 2 should always be programmed
in the order specified in the Initialization Sequence section.
To program the frequency of the ADRF6601, the user typically
programs only Register 0, Register 1, and Register 2. However,
if registers other than these are programmed first, a short delay
should be inserted before programming Register 0. This delay
ensures that the VCO band calibration has sufficient time to com-
plete before the final band calibration for Register 0 is initiated.
Software is available on the ADRF6601 product page of the
Analog Devices website (www.analog.com) that allows easy
programming from a PC running Windows XP or Vista.
INITIALIZATION SEQUENCE
To ensure proper power-up of the ADRF6601, it is important to
reset the PLL circuitry after the VCC supply rail settles to 5 V ±
0.25 V. Resetting the PLL ensures that the internal bias cells are
properly configured, even under poor supply start-up conditions.
To ensure that the PLL is reset after power-up, follow these steps:
1.
2.
After this procedure is followed, the other registers should be
programmed in this order: Register 7, Register 6, Register 4,
Register 3, Register 2, Register 1. Then, after a delay of >100 ms,
Register 0 should be programmed.
Disable the PLL by setting the PLEN bit to 0 (Register 5,
Bit DB6).
After a delay of >100 ms, set the PLEN bit to 1.
Function
Integer divide control for the PLL
Modulus divide control for the PLL
Fractional divide control for the PLL
Σ-Δ modulator dither control
PLL charge pump, PFD, reference path control
PLL enable and LO path control
VCO control and VCO enable
Mixer bias enable and external VCO enable
ADRF6601