ADRF6750 Analog Devices, Inc., ADRF6750 Datasheet - Page 25

• Manufacturer Part Number: ADRF6750
• Description: 950 Mhz To 1575 Mhz Quadrature Modulator With Integrated Fractional-n Pll And Vco
• Manufacturer: Analog Devices, Inc.

PROGRAM MODES
The ADRF6750 has 34 8-bit registers to allow program control
of a number of functions. Either an SPI or an I
can be used to program the register set. For details about the
interfaces and timing, see Figure 63 to Figure 69. The registers
are documented in Table 6 to Table 24.
Several settings in the ADRF6750 are double-buffered. These
settings include the FRAC value, the INT value, the 5-bit
R-divider value, the reference frequency doubler, the R/2
divider, and the charge pump current setting. This means that
two events must occur before the part uses a new value for
any of the double-buffered settings. First, the new value is
latched into the device by writing to the appropriate register.
Next, a new write must be performed on Register CR0. When
Register CR0 is written, a new PLL acquisition takes place.
For example, updating the fractional value involves a write to
Register CR3, Register CR2, Register CR1, and Register CR0.
Register CR3 should be written to first, followed by Register CR2
and Register CR1 and, finally, Register CR0. The new acquisition
begins after the write to Register CR0. Double buffering ensures
that the bits written to do not take effect until after the write to
Register CR0.
12-Bit Integer Value
Register CR7 and Register CR6 program the integer value (INT)
of the feedback division factor. The INT value is a 12-bit number
whose MSBs are programmed through Register CR7, Bits[3:0].
The LSBs are programmed through Register CR6, Bits[7:0]. The
INT value is used in Equation 1 to set the LO frequency. Note
that these registers are double-buffered.
25-Bit Fractional Value
Register CR3 to Register CR0 program the fractional value
(FRAC) of the feedback division factor. The FRAC value is a
25-bit number whose MSB is programmed through Register CR3,
Bit 0. The LSB is programmed through Register CR0, Bit 0. The
FRAC value is used in Equation 1 to set the LO frequency. Note
that these registers are double-buffered.
Reference Input Path
The reference input path consists of a reference frequency doubler,
a 5-bit reference divider, and a divide-by-2 function (see Figure 53).
The doubler is programmed through Register CR10, Bit 5. The
5-bit divider is enabled by programming Register CR5, Bit 4,
and the division ratio is programmed through Register CR10,
Bits[4:0]. The R/2 divider is programmed through Register CR10,
Bit 6. Note that these registers are double-buffered.
When using a 10 MHz reference input frequency, enable the
doubler and disable the 5-bit divider and divide-by-2 to ensure
a PFD frequency of 20 MHz. As mentioned in the Reference
Input Path section, making the PFD frequency higher improves
the system noise performance.
2
C interface
Rev. 0 | Page 25 of 40
Charge Pump Current
Register CR9, Bits[7:4], specify the charge pump current
setting. With an R
pump current is 5 mA. The following equation applies:
The charge pump current has 16 settings from 312.5 μA to 5 mA.
For the loop filter that is specified in the application solution, a
charge pump current of 2.5 mA (Register CR9[7:4] = 7) gives a
loop bandwidth of 50 kHz, which is the recommended loop
bandwidth setting.
Transmit Disable Control (TXDIS)
The transmit disable control (TXDIS) is used to disable the RF out-
put. TXDIS is normally held low. When asserted (brought high), it
disables the RF output. Register CR14 is used to control which
circuit blocks are powered down when TXDIS is asserted. To meet
both the off isolation power specifications and the turn-on/
turn-off settling time specifications, a value of 0x1B should be
loaded into Register CR14. This effectively ensures that the
attenuator is always enabled when TXDIS is asserted, even if other
circuitry is disabled.
Power-Down/Power-Up Control Bits
The three programmable power-up and power-down control
bits are as follows:
•
•
•
Lock Detect (LDET)
Lock detect is enabled by setting Register CR23, Bit 4, to 1.
Register CR23, Bit 3 sets the number of up/down pulses
generated by the PFD before lock detect is declared. The default
is 3072 pulses, which is selected when Bit 3 is set to 0. A more
aggressive setting of 2048 is selected when Bit 3 is set to 1. This
improves the lock detect time by 50 μs. Note, however, that it
does not affect the acquisition time to 100 Hz. Register CR23,
Bit 2 should be set to 0 for best operation. This bit sets up the
PFD up/down pulses to a coarse or low precision setting.
I
Register CR12, Bit 2. Master power control bit for the PLL,
including the VCO. This bit is normally set to a default
value of 0 to power up the PLL.
Register CR27, Bit 2. Controls the LO monitor outputs,
LOMONP and LOMONN. The default is 0 when the monitor
outputs are powered down. Setting this bit to 1 powers up
the monitor outputs to one of −6 dBm, −12 dBm, −18 dBm,
or −24 dBm, as controlled by Register CR27, Bits[1:0].
Register CR29, Bit 0. Controls the quadrature modulator
power. The default is 0, which powers down the modulator.
Write a 1 to this bit to power up the modulator.
CPmax
= 23.5/R
SET
SET
value of 4.7 kΩ, the maximum charge
ADRF6750