IRM7001 Vishay, IRM7001 Datasheet - Page 7

• Manufacturer Part Number: IRM7001
• Description: Sir Modulator/demodulator
• Manufacturer: Vishay

IRDA-SIR Encoding and Decoding Scheme
Overview of Encoding Scheme
Figures 5 and 6 outline the IRDA-SIR encoding
scheme. The encoding scheme relies on a clock
being present, which is set to 16 times the data
transmission baud rate (16XCLK).
The encoder sends a pulse for every space (0) that
is sent. On a high to low transition of the TXD line,
the generation of the pulse is delayed for 7 clock
cycles of the 16XCLK clock before the pulse is set
high for 3 clock cycles (or 3/16 of a bit time) and
subsequently pulled low. This in essence generates
a 3/16th bit time pulse centered around the bit of
information (0) that is being transmitted.
For consecutive spaces, pulses with a 1 bit time
delay are generated in series. If a logic 1 (mark) is
sent, then the encoder does not generate a pulse.
Overview of the Decoding Scheme
The IRDA-SIR decoding modulation method can be
thought of as a pulse stretching scheme:
Every high to low transition of the IR-RXD line signi-
fies the arrival of a 3/16th pulse. This pulse needs to
be stretched to accommodate 1 bit time (or 16
16XCLK cycles). Every pulse that is received is
translated into a'O' or space on the RXD line. If a
series of pulses separated by 1 bit time are
received, then the net result is a I bit time low pulse
for every 3/16th pulse received (see figure 9).
To be correctly received and interpreted by a UART,
the stretched pulse must be at least 3/4 of a bit time
in duration.
Document Number: 82576
Revision 17-August-01
Figure 6. Encoding Scheme—Macro Perspective
Figure 7. IrDA-SIR Encoding Scheme—Detailed Timing Diagram
Figure 8. Decoding Scheme—Macro Perspective
Figure 9. IrDA-SIR Decoding Scheme—Detailed Timing Diagram
16 XCLK
IRRXD
RXD
16 XCLK
TXD
IRTXD
16XCLK
16XCLK
IRRXD
RXD
IRTXD
TXD
7 CS
16 Cycles
16 Cycles
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 CS
16 Cycles
16 Cycles
16 Clock Cycles = 1 Bit Time
3 CS
16 Cycles
16 Cycles
16 Cycles
16 Cycles
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