LTC2630-10 Linear Technology Corporation, LTC2630-10 Datasheet - Page 14

• Manufacturer Part Number: LTC2630-10
• Description: Ltc2630-10 - Single 10-bit Rail-to-rail Dacs With Integrated Reference In Sc70
• Manufacturer: Linear Technology Corporation

OPERATION
LTC2630
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, enabling the SDI and
SCK buffers and the input shift register. Data (SDI input)
is transferred at the next 24 rising SCK edges. The 4-bit
command, C3-C0, is loaded fi rst; then 4 don’t-care bits;
and fi nally the 16-bit data word. The data word comprises
the 12-, 10- or 8-bit input code, ordered MSB-to-LSB, fol-
lowed by 4, 6 or 8 don’t-care bits (LTC2630-12, -10 and -8
respectively; see Figure 2). Data can only be transferred
to the device when the CS/LD signal is low, beginning on
the fi rst rising edge of SCK. SCK may be high or low at
the falling edge of CS/LD. The rising edge of CS/LD ends
the data transfer and causes the device to execute the
command specifi ed in the 24-bit input sequence. The
complete sequence is shown in Figure 3a.
The command (C3-C0) assignments are shown in Table 1.
The fi rst three commands in the table consist of write and
update operations. A Write operation loads a 16-bit data
word from the 24-bit shift register into the input register.
In an Update operation, the input register is copied to the
DAC register and converted to an analog voltage at the
DAC output. Write to and Update combines the fi rst two
commands. The Update operation also powers up the
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
14
INPUT WORD (LTC2630-12)
INPUT WORD (LTC2630-10)
INPUT WORD (LTC2630-8)
C3
C3
C3
COMMAND
COMMAND
COMMAND
C2
C2
C2
C1
C1
C1
C0
C0
C0
X
X
X
4 DON'T-CARE BITS
4 DON'T-CARE BITS
4 DON'T-CARE BITS
X
X
X
X
X
X
Figure 2. Command and Data Input Format
X
X
X
MSB
MSB
MSB
D11 D10
D9
D7
D8
D6
D9
D7
D5
D8
D6
D4
While the minimum input sequence is 24 bits, it may
optionally be extended to 32 bits to accommodate micro-
processors that have a minimum word width of 16 bits
(2 bytes). To use the 32-bit width, 8 don’t-care bits are trans-
ferred to the device fi rst, followed by the 24-bit sequence
described. Figure 3b shows the 32-bit sequence.
The 16-bit data word is ignored for all commands that do
not include a Write operation.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the
DAC output is not needed. When in power-down, the buffer
amplifi er, bias circuit, and reference circuit are disabled and
draw essentially zero current. The DAC output is put into
a high-impedance state, and the output pin is passively
pulled to ground through a 200kΩ resistor. Input and DAC
register contents are not disturbed during power-down.
The DAC can be put into power-down mode by using
command 0100. The supply current is reduced to 1.8μA
maximum when the DAC is powered down.
Normal operation resumes after executing any command
that includes a DAC update, as shown in Table 1. The DAC
is powered up and its voltage output is updated. Normal
settling is delayed while the bias, reference, and amplifi er
circuits are re-enabled. The power up delay time is 18μs
for settling to 12 bits.
D7
D5
D3
DATA (12 BITS + 4 DON'T-CARE BITS)
DATA (10 BITS + 6 DON'T-CARE BITS)
DATA (8 BITS + 8 DON'T-CARE BITS)
D6
D4
D2
D5
D3
D1
LSB
D4
D2
D0
D3
D1
X
LSB
D2
D0
X
D1
X
X
LSB
D0
X
X
X
X
X
X
X
X
X
X
X
2630 F02
X
X
X
2630fb