NP3750 Applied Micro Circuits Corporation (AMCC), NP3750 Datasheet - Page 2

• Manufacturer Part Number: NP3750
• Description: Np3750 5-gbps Network Processor With Integrated Traffic Manager
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

nP3750
nP3750 Highlights
Interfaces
• Line Interfaces – cell and packet
• Fabric Interface: OIF SPI-4 Phase 2
• External Memory Interfaces:
SPI3/UT3
SPI3/UT3
nP3750
– 800 MHz
RLDRAM II memory controllers
– Payload Memory:
GE
GE
GE
GE
GE
GE
GE
GE
GE
GE
GE
GE
Two banks of 36-bit RLDRAM II
operating at up to 250 MHz (32 Gbps
with ECC)
SPI-3/UT-3
1
NPF(QDR)
NPF(QDR)
NPF(QDR)
NPF(QDR)
Interfaces
Interfaces
Interfaces
Interfaces
18
18
18
18
16-bit
16-bit
Engine
Engine
Engine
Engine
GE
Policy
Policy
Policy
Policy
4
(CSM)
(CSM)
(CSM)
(CSM)
FE/GE
FE/GE
FE/GE
FE/GE
MACs
MACs
MACs
MACs
Line
Line
Line
Line
HOST CPU
HOST CPU
HOST CPU
HOST CPU
SPI-4.2
1
36
36
36
36
3 nPcores @ 700 MHz
3 nPcores @ 700 MHz
QDR
QDR
QDR
QDR
Statistics
Statistics
Statistics
Statistics
SPU
SPU
SPU
SPU
nPcore @ 700 MHz
nPcore @ 700 MHz
nPcore @ 700 MHz
nPcore @ 700 MHz
Engine
Engine
Engine
Engine
• CPU Interfaces: PowerPC and Gigabit
• External Search Interface
• Debug port
• JTAG port
36
36
36
36
– Context Memory:
– Channel Service Memory:
– Flow Database Memory:
Ethernet
– Compliant with NPF
– Backward compatibility mode with
Packet Transform
Packet Transform
Packet Transform
Packet Transform
Two banks of 36-bit RLDRAM II
operating at up to 250 MHz (32 Gbps
with ECC)
One bank of 36-bit QDR-II SRAM
operating at up to 250 MHz
Two banks of 18-bit QDR-II SRAM
operating at up to 250 MHz
existing TCAMs
72 Tasks
72 Tasks
nP3750 Block Diagram
Memory Access Unit
24 Tasks
24 Tasks
24 Tasks
24 Tasks
Memory Access Unit
Memory Access Unit
Memory Access Unit
Memory Access Unit
Engine
Engine
Engine
Engine
Cache
Cache
DRAM/SRAM
DRAM/SRAM
(PTE)
(PTE)
(PTE)
(PTE)
DEBUG
DEBUG
XSC
XSC
XMI
XMI
DEBUG
DEBUG
36
36
36
36
RLDRAM
RLDRAM
36
36
36
36
Engine
Engine
Engine
Engine
Hash
Hash
Hash
Hash
FCN
FCN
36
36
36
36
Soft TM
Soft TM
Soft TM
Soft TM
High Performance nPcore
• Three nPcores at up to 700 MHz
Integrated Coprocessors
• Policy Engine for efficient packet
• Special Purpose Unit (SPU) for per-flow
• Hashing Unit
• On-Chip Debugger (OCD)
Integrated Traffic Manager
• Hierarchical Traffic Manager with
• Leverages field-proven nPX5710 and
Manager
Manager
Manager
Manager
classification
policing
fine-grained flow-based traffic
management
nPX5720 technology
DRAM
RLDRAM
DRAM
RLDRAM
Scheduling
Scheduling
Scheduling
Scheduling
Traffic
Traffic
Traffic
Traffic
Queuing
Queuing
Queuing
Queuing
36
36
36
36
JTAG
JTAG
JTAG
JTAG
Scratch
Scratch
Scratch
Scratch
Pad
Pad
Pad
Pad
SPI4.2
SPI4.2
SPI4.2
SPI4.2