TUA4401K Infineon Technologies Corporation, TUA4401K Datasheet
TUA4401K
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TUA4401K Summary of contents
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Wireless Components FM Car Radio IC with PLL TUA 4401K V 2.1 Specification 17.02. ...
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Revision History: Current Version: 02.00 Previous Version:Data Sheet 23.09.1999 Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) 3-7 3-7 Functional description pin 41 corrected 3-11 3-11 Functional description pin 41 corrected 5-3 5-3 Sequence ...
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Productinfo General Description The TUA 4401K is the first Infineon Carradio IC using BICMOS technol- ogy. The combination of an analog FM receiver circuit and a digital PLL syn- thesizer on the same chip reduces the over all pin count ...
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Table of Contents 1 Table of Contents 2 Product Description 2.1 General Description 2.2 Applications 2.3 Features 2.4 Package Outlines 3 Functional Description 3.1 Pin Configuration 3.2 Block Diagram 3.3 Functional Block Diagram 3.4 Circuit Description 4 Applications 4.1 ...
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Product Description Contents of this Chapter 2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General Description The TUA 4401K is the first Infineon Carradio IC using BICMOS technology. The combination of an analog FM receiver circuit and a digital PLL synthesizer on the same chip reduces the over all pin count in comparison ...
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I C Bus bus (2 wire, fast mode device with 400 kbit/s) operation possible Bus interface with low threshold voltage Schmitt Trigger inputs for interfac- ing microprocessors 2.2 Applications FM only ...
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Package Outlines MQFP 44 Wireless Components Product Description Specification, 17.02.00 TUA 4401K ...
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Functional Description Contents of this Chapter 3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Configuration Figure 3-1 Table 3-1 Pin Configuration Pin No. Symbol 1 1 FS_ADC 2 MPA_ADC 2 Wireless Components ...
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Table 3-1 Pin Configuration (continued) Pin No. Symbol 3 Station_Detect 4 SCL 5 SDA 6 VREFD5V 7 VREFD3V XTAL_DIV6 Wireless Components Equivalent I/O-Schematic + ...
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Table 3-1 Pin Configuration (continued) Pin No. Symbol 9 PORT_2 QUARTZ1 QUARTZ2 12 VCCD 13 GNDD 14 PORT_1 Wireless Components Equivalent I/O-Schematic + ...
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Table 3-1 Pin Configuration (continued) Pin No. Symbol 15 PDA PD_0 17 GNDRF Wireless Components Equivalent I/O-Schematic PDA + ...
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Table 3-1 Pin Configuration (continued) Pin No. Symbol + OSC1 19 OSC2 20 VCCRF PRE_CAP Wireless Components Equivalent I/O-Schematic + TUA ...
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Table 3-1 Pin Configuration (continued) Pin No. Symbol 22 FM1 FM2 AGCOUT_P Wireless Components Equivalent I/O-Schematic TUA 4401K ...
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Table 3-1 Pin Configuration (continued) Pin No. Symbol 25 IF2 IF1 VREFRF 28 GNDIF1 IFINFM IFIN Wireless Components Equivalent I/O-Schematic ...
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Table 3-1 Pin Configuration (continued) Pin No. Symbol 31 IFOUTFM IFAMPC 33 VCCIF FMIFIN FMIFBIAS 36 GNDIF2 Wireless Components Equivalent I/O-Schematic + ...
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Table 3-1 Pin Configuration (continued) Pin No. Symbol 37 MPXOUT + V 38 FSOUT 39 MPA_IN Wireless Components Equivalent I/O-Schematic + ...
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Table 3-1 Pin Configuration (continued) Pin No. Symbol 40 MPACAP 41 MPA_OUT 42 DEMAFC 43 PH02 PH01 Wireless Components Equivalent I/O-Schematic + ...
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Block Diagram ...
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Functional Block Diagram in det MP out MPX Figure 3-3 Wireless Components Functional Block Diagram TUA 4401K Functional Description Station_Detect CCD SDA SCL Funct_block.wmf Specification, 17.02.00 ...
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Circuit Description The TUA 4401K is a one chip FM car radio system consisting of RF frontend, gain adjustable IF amplifier, FM-IF limiter amplifier, demodulator, PLL synthe- sizer, IF counter for STS and ADC’s for fieldstrength and multipath detector. ...
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... PORT_1 / 2 are NMOS Open drain outputs Bus The TUA4401K supports the I SDA) are Schmitt triggered input buffer for The bit stream begins with the most significant bit (MSB), is shifted in (write mode) on the low to high transition of CLK and is shifted out (read mode) on ...
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Acknowledge (ACK): Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data. During the 9th clock cycle the receiver will pull the SDA line to low level to indicate it has receive the ...
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Applications Contents of this Chapter 4.1 Application and Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Application and Circuits FM only car radio receiver, background receiver 10uH 100 1uH BAR63 22k 1k 4,7k 22k 33k 150p 3,3k 3,3k 10k Figure 4-1 Wireless Components 1k 10n 10 330 100 4,7k 22n 51 1k 330 100uH ...
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Figure 4-2 Wireless Components Application Circuit TUA 4401K Applications 4401K_SPEC.eps Specification, 17.02.00 ...
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Reference Contents of this Chapter 5.1 Electrical Data ...
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Electrical Data 5.1.1 Absolute Maximum Range The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the IC will result. Table 5-1 Absolute Maximum Range Parameter ESD-Protection all bipolar pins ...
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AC/DC Characteristics characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Table 5-3 AC/DC Characteristics with T Symbol Power Supply Total ...
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Table 5-3 AC/DC Characteristics with T Symbol AGC current normal polarity I 24 Integrator current I 21 Integrator current amplifier DC input voltage V 29 Input resistance R 29 Output resistance R 31 Max. Voltage gain A ...
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Table 5-3 AC/DC Characteristics with T Symbol Multipath detector Attack current I 40 Recovery current I 40 Start voltage V 41Def Detector characteristic Detector currents are measured between the output pin (-pole) and a voltage source V ...
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Table 5-3 AC/DC Characteristics with T Symbol HIGH output current source I PDA_H LOW output current source I PDA_L PLL for synthesizer (see PLL Synthesizer on page 3-16) PLL / VCO step size f ref (programmable via R- counter) N-counter ...
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Phase detector outputs P-Channel PD_O Tri-State. Polarity N-Channel pos. Frequency lagging V Wireless Components < f Frequency f > leading TUA ...
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Bus Interface 1. Bus Interface Bus 2. Bus Data Format Bus Write Mode CHIP ADDRESS (WRITE) MSB LSB STA ACK Bus Read ...
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Data Byte Specification Status Subaddress 00H Bit Function MSB D15 not used (must be=0) D14 Port_2 (0=low, 1=high) D13 Port_1 (0=low, 1=high) D12 not used (must be=0) D11 Loopamp current D10 not used (must be=0) D9 not used (must be=0) ...
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D1 Res D0 Res LSB Status, Subaddress 00H MSB LSB MSB D15 D14 D13 D12 D11 D10 ...
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Subaddress 03H, Mute_DAC7 MSB LSB Function not used (must be 1) Subaddress 04H, IF_Count_P1 MSB LSB Function ...
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Subaddress 06H, Specials MSB LSB Function XTAL_DIV6 enabled 0 XTAL_DIV6 disabled 1 1st LO divided 1st LO divided by 2 Prest. AGC threshold typ ...
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Subaddress 82H, Read results from Fieldstrength, Multipath and IF counter MSB LSB MSB D15 D14 D13 D12 D11 D10 5.4 ...
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Table 5-4 Parameter LOW level input voltage (SDA, SCL) HIGH level input voltage (SDA, SCL) Pulse width of spikes which must be suppressed by the input fil- ter LOW level output voltage 3mA sink current (SDA) Output fall time from ...