MBM29F160TE Fujitsu Microelectronics, Inc., MBM29F160TE Datasheet - Page 22

• Manufacturer Part Number: MBM29F160TE
• Description: 16m 2m X 8/1m X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

MBM29F160TE
RY/BY
Ready/Busy Pin
RESET
Hardware Reset Pin
Byte/Word Configuration
Data Protection
Low V
22
Furthermore, DQ
mode, DQ
The MBM29F160TE/BE provides a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy
with either a program or erase operation. If the output is high, the device is ready to accept any read/write or
erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29F160TE/BE is placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. See Figure 11 and 12 for a detailed timing diagram.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
The MBM29F160TE/BE device may be reset by driving the RESET pin to V
requirement and has to be kept low (V
operation in the process of being executed will be terminated and the internal state machine will be reset to the
read mode t
requires an additional t
standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset
occurs during a program or erase operation, the data at that particular location will be corrupted. Please note
that the RY/BY output signal should be ignored during the RESET pulse. Refer to Figure 12 for the timing
diagram. Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will
need to be erased again before they can be programmed.
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29F160TE/BE device. When this
pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ
DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
Figures 13 and 14 for the timing diagrams.
The MBM29F160TE/BE is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequence.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
To avoid initiation of a write cycle during V
than 3.2 V (typically 3.7 V). If V
are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
15
CC
. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ
CC
Write Inhibit
level is greater than V
2
toggles if this bit is read from an erasing sector.
READY
2
after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device
can also be used to determine which sector is being erased. When the device is in the erase
RH
before it allows read access. When the RESET pin is low, the device will be in the
LKO
CC
-55/-70/-90
. It is the users responsibility to ensure that the control pins are logically correct
< V
LKO
IL
, the command register is disabled and all internal program/erase circuits
CC
) for at least t
8
to DQ
is above 3.2 V.
CC
power-up and power-down, a write cycle is locked out for V
14
/MBM29F160BE
bits are tri-stated. However, the command bus cycle is always
RP
in order to properly reset the internal state machine. Any
0
to DQ
7
and DQ
8
IL
to DQ
. The RESET pin has a pulse
15
-55/-70/-90
bits are ignored. Refer to
15
CC
/A
power-up
-1
pin
CC
CC
less
0
.
to