MX29LV033A ETC-unknow, MX29LV033A Datasheet - Page 9

• Manufacturer Part Number: MX29LV033A
• Description: 32m-bit [4m X 8] Cmos Equal Sector Flash Memory
• Manufacturer: ETC-unknow

cally 0.2uA (CMOS level).
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output
from the devices are disabled. This will cause the output
pins to be in a high impedance state.
RESET# OPERATION
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the RESET# pin
is driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write
commands for the duration of the RESET# pulse. The
device also resets the internal state machine to reading
array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS 0.3V, the device draws
CMOS standby current (ICC4). If RESET is held at VIL
but not within VSS 0.3V, the standby current will be
greater.
The RESET# pin may be tied to system reset circuitry.
A system reset would that also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains a "0" (busy) until the
internal reset operation is complete, which requires a time
of tREADY (during Embedded Algorithms). The system
can thus monitor RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
program or erase operation is completed within a time of
tREADY (not during Embedded Algorithms). The system
can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 3 for the timing diagram.
SECTOR GROUP PROTECT OPERATION
The MX29LV033A features hardware sector group pro-
tection. This feature will disable both program and erase
P/N:PM1017
9
operations for these sector group protected. To activate
this mode, the programming equipment must force VID
on address pin A9 and control pin OE#, (suggest VID =
12V) A6 = VIL and CE# = VIL. (see Table 2) Program-
ming of the protection circuitry begins on the falling edge
of the WE# pulse and is terminated on the rising edge.
Please refer to sector group protect algorithm and wave-
form.
MX29LV033A also provides another method. Which re-
quires VID on the RESET# only. This method can be imple-
mented either in-system or via programming equipment.
This method uses standard microprocessor bus cycle
timing.
To verify programming of the protection circuitry, the pro-
gramming equipment must force VID on address pin A9
( with CE# and OE# at VIL and WE# at VIH). When
A1=1, it will produce a logical "1" code at device output
Q0 for a protected sector. Otherwise the device will pro-
duce 00H for the unprotected sector. In this mode, the
addresses, except for A1, are don't care. Address loca-
tions with A1 = VIL are reserved to read manufacturer
and device codes. (Read Silicon ID)
It is also possible to determine if the group is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
CHIP UNPROTECTED OPERATION
The MX29LV033A also features the chip unprotected
mode, so that all sectors are unprotected after chip
unprotected is completed to incorporate any changes in
the code. It is recommended to protect all sectors before
activating chip unprotected mode.
To activate this mode, the programming equipment must
force VID on control pin OE# and address pin A9. The
CE# pins must be set at VIL. Pins A6 must be set to
VIH.(see Table 2) Refer to chip unprotected algorithm
and waveform for the chip unprotected algorithm. The
unprotected mechanism begins on the falling edge of the
WE# pulse and is terminated on the rising edge.
MX29LV033A also provides another method. Which re-
quires VID on the RESET# only. This method can be imple-
mented either in-system or via programming equipment.
This method uses standard microprocessor bus cycle
timing.
MX29LV033A
REV. 1.0, SEP. 20, 2004