SCANSTA101 National Semiconductor Corporation, SCANSTA101 Datasheet
SCANSTA101
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SCANSTA101 Summary of contents
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... SCANSTA101 Low Voltage IEEE 1149.1 STA Master General Description The SCANSTA101 is designed to function as a test master for a IEEE 1149.1 test system. The minimal requirements to create a tester are a microcomputer (uP, RAM/ROM, clock, etc.), SCANEASE r2.0 software, and a STA101. The SCANSTA101 is an enhanced version of, and replace- ment for, the SCANPSC100 ...
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... Figure 1 shows a high level view of the SCANSTA101 Scan Master and its interface groups. Table 1 provides a brief de- scription of each of these interface groups. Table 2 provides a brief description of the external interfaces. The device is composed of three interfaces around a dual-port memory. These interfaces consist of the Parallel Processor Interface ...
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TABLE 2. Pin Descriptions Pin Name No. Pins I/O VCC 4 N/A 4 N/A GND 16 I/O D(15:0) D(31:16) 16 I/O (Note 1) A(4: SCK INT DTACK 1 O R/W 1 STB 1 1 ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Input Diode Current ( −0. Input Voltage ...
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AC Electrical Characteristics/Operating Requirements supply voltage and temperature ranges unless otherwise specified. C Symbol Parameter PARALLEL PROCESSOR INTERFACE (PPI) t Set Up Time S1 CE, R/W, Addr, Data to STB t Hold Time H1 CE, R/W, Addr, Data to DTACK ...
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Symbol Parameter SERIAL SCAN INTERFACE (SSI) t Propagation Delay D5 SCK to TCK_SM t Propagation Delay D6 SCK to TDO_SM t Propagation Delay D7 SCK to TMS_SM t Propagation Delay - tpLH D8 SCK to TRIST_SM t Propagation Delay - ...
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Symbol Parameter TEST & DEBUG INTERFACE TIMING REQUIREMENTS (SCAN) t Setup Time S TMS to TCK t Hold Time H TMS to TCK t Setup Time S TDI to TCK t Hold Time H TDI to TCK t Pulse Width ...
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Applications/Programmers Reference Address Type Mnemonic 00h RW START 01h RW STATUS 02h RW INTCTRL 03h RW INTSTAT 04h RW SETUPR 05h RW CLKDIV 07h RW EXPR 08h RW LSSEDR 09h RW MSSEDR 0Ah RW LSRESR 0Bh RW MSRESR 0Ch RW ...
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Function Macro Index Macro 1 Macro 2 Macro Macro Sequencer Index ...
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Bit 2 Bit 1 Bit 0 Function Ignore Headers and Trailers Use Instruction Header Use Instruction Trailer Use both Instruction Header and Trailer Use Data ...
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The only area were this could occur in memory would be the TDI_SM memory space since both the SSI and PPI can write to this space, but the drivers shouldn't ...
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... SSI indicate to the FG when the SSI's pointer value has changed decrement and an increment occur at the same time to either of the counters, the counter value will not change. PPI INTERFACE TIMING The processor accesses to SCANSTA101 can be classified into six categories: • register read • ...
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SHIFTER The Shifter block contains two 32-bit shift registers for TDO_SM and TDI_SM respectively, and one 16-bit shift reg- ister for TMS_SM. The TMS_SM shifter block diagram is shown in Figure 2, the TDO_SM shifter block diagram is shown in ...
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The TDI_SM shifter unit consists of two 32-bit shift registers as shown in Figure 4. The shift register on top will be used as an LFSR register. However, before using the TDI_SM LFSR register, the LFSR Exponent and LFSR Seed ...
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TABLE 12. Compare and Use Mask/Compare Bit Descriptions Compare Results of Compare bit (bit 15 of Status register) stores the comparison results in the status register. This bit defaults to fail (zero) and will be updated ...
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Repeat Steps 1b through 1g to configure the ScanBridges in the remaining hierarchy levels. One set of pre-PAD and post-PAD bits is added to the patterns for each hierarchy level between the ScanMaster and the ScanBridge being configured. The ...
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If the TAP tracker is in the Shift-IR state and the number of levels of hierarchy is greater than one, set the count length to eight, and drive TDO_SM with post-PAD bits (all high) until the count length is ...
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FIGURE 8. Timing from Mode Register to Sequencer Start WRITING AND READING PARTIAL LONG WORDS Care should be taken when writing a partial long word to TDO_SM memory or reading a partial long word from TDI_SM memory. Since the TDO_SM ...
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SETUP[11:10] TDO_SM 00 Hold Previous value Default TDO value (Bit 6 of the SETUP register) (Note 10) 11 High Impedance Note 10: Default TDO value (bit 6 of the SETUP register) may be set ...
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Signal Name No. Pin Type TDI_SM 1 I TDO_SM 1 O TMS_SM 1 O TCK_SM 1 O TRST0_SM 1 O TRST1_SM 1 O TRIST_SM 1 O www.national.com TABLE 16. Serial Scan Interface Signal Descriptions Driver Type Freq. MHz LVTTL up ...
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FIGURE 13. SSI Timing Diagram with Clock Divider set to 4 FIGURE 14. SSI Timing Diagram with Clock Divider set to 8 Signal Name No. of Pin Type Bits TDO 1 O TDI 1 I,U TMS 1 I,U TCK 1 ...
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Signal Name No. of Pin Type Bits SCAN_EN 1 I SCAN_IN 1 I SCAN_OUT 1 O TEST AND DEBUG INTERFACE The test and debug interfaces are provided to perform man- ufacturing tests. There is a standard JTAG interface along with ...
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REGISTER DEFINITIONS The following sections include descriptions of each address- able register in the ScanMaster memory space. Following the title of the particular register, the mnemonic for the register is Bit(s) Type 15:14 RO Reserved 13 RW Onboard Memory BIST ...
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Bit(s) Type 15 RW Results of Compare (Note 13 BIST Running 13 RW Memory BIST Result 12 RW TDO Status Half-empty (Note 15 TDO Status Empty 10 RW TDI Status Full 9 RW TDI Status Half-full ...
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TABLE 21. Interrupt Control Register (INTCTRL) ($02) Bit(s) Type 15:13 RO Reserved 12 RW TDO Half-empty Interrupt Enable (Note 18 TDO Empty Interrupt Enable 10 RW TDI Full Interrupt Enable 9 RW TDI Half-full Interrupt Enable (Note 18) ...
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TABLE 22. Interrupt Status Register (INTSTAT) ($03) (Note 22) Bit(s) Type 15:13 RO Reserved 12 RW TDO Half-empty Interrupt (Note 21 TDO Empty Interrupt 10 RW TDI Full Interrupt 9 RW TDI Half-full Interrupt (Note 21 ...
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Bit(s) Type 15 RW 16/32 bit Mode 14:10 RO Reserved 11:10 RW TDO_SM Ctrl 9:7 RW Sync Bit Length 6 RW Default TDO Value 5 RW Debug Mode 4 RW ScanBridge Support Initiate/ Release 3 RW TRST 2 RW Reset ...
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Bit(s) Type 15:8 RO Reserved 7:1 RW Divisor 0 RO Reserved (hard coded) (Note 23) Note 23: LSB of the Clock Divider register is hard coded to zero. Divisor<7:1> '0000000' '0000001' '0000010' '0000100' '0001000' '0010000' '0100000' '1000000' TABLE 25. TDI_SM ...
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TABLE 29. TDI_SM LFSR MSB Result Register (MSRESR) ($0B) (Notes 30, 31) Bit(s) Type 15:0 RW MSW LFSR Result Note 30: MSW LFSR Result<15:0> is the MS word of the LFSR result. Note 31: This register along with register LSRESR ...
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An 8 instruction Tap Controller will be used to accomplish the IEEE 1149.1 support design. Instruction Mnemonic Binary Instruction Code EXTEST 000 SAMPLE/PRELOAD 001 BYPASS 111 IDCODE 010 HIGHZ 011 CLAMP 100 RUNBIST 110 SCANTEST 101 Version "0000" "1111 1100 ...
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... Physical Dimensions inches (millimeters) unless otherwise noted (Tape and Reel Ordering Code SCANSTA101SMX) 49-Pin BGA NS Package Number SLC49A Ordering Code SCANSTA101SM 31 www.national.com ...
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