PI6CV857 Pericom Semiconductor Corporation, PI6CV857 Datasheet

PI6CV857

Manufacturer Part Number

PI6CV857

Description

2.5v, 170 Mhz, 10 Output Sstl-2 Zero Delay Clock Driver, High Drive For Stacked Ddr Dimm

Manufacturer

Pericom Semiconductor Corporation

Datasheet

1.PI6CV857.pdf (10 pages)

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Block Diagram/Pin Configuration

Product Features

• PLL clock distribution optimized for Double Data Rate

• Distributes one differential clock input pair to ten differential

• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2

• Input PWRDWN: LVCMOS

• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2

• External feedback pins (FBIN,FBIN) are used to

• Operates at AV

• Package: Plastic 48-pin TSSOP (A)

SDRAM applications.

clock output pairs.

synchronize the outputs to the clock input.

and V

PWRDWN

AV DD

FBIN

CLK

DDQ

= 2.5V for differential output drivers

= 2.5V for core circuit and internal PLL,

Powerdown

and Test

Logic

PLL

FBOUT

Product Description

PI6CV857 PLL clock device is developed for registered DDR DIMM

applications This PLL Clock Buffer is designed for 2.5 V

Package options include plastic Thin Shrink Small-Outline Package

(TSSOP).The device is a zero delay buffer that distributes a differ-

ential clock input pair (CLK, CLK) to ten differential pairs of clock

outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock

outputs (FBOUT,FBOUT) . The clock outputs are controlled by the

input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V

LVCMOS input (PWRDWN) and the Analog Power input (AV

When input PWRDWN is low while power is applied, the input

receivers are disabled, the PLL is turned off and the differential clock

outputs are 3-stated. When the AV

turned off and bypassed for test purposes.

When the input frequency falls below a suggested detection fre-

quency that is below the operating frequency of the PLL, the device

will enter a low power mode. An input frequency detection circuit will

detect the low frequency condition and perform the same low power

features as when the PWRDWN input is low.

The PLL in the PI6CV857 clock driver uses input clocks (CLK, CLK)

and feedback clocks (FBIN,FBIN) to provide high-performance, low-

skew, low-jitter output differential clocks (Y[0:9], Y[0:9]). PI6CV857

is also able to track Spread Spectrum Clocking for reduced EMI.

operation and differential data input and output levels.

AG N D

V D D Q

AV D D

V D D Q

G N D

C L K

Y 0

Y 1

Y 2

Y 3

Y 4

2.5V DDR-SDRAM Memory

48-Pin

PLL Clock Driver for

is strapped low, the PLL is

G N D

Y 5

V D D Q

Y 6

G N D

Y 7

V D D Q

P W R D W N

FBIN

V D D Q

F B O U T

G N D

Y 8

V D D Q

Y 9

G N D

PI6CV857

PS8464D

DDQ

and 2.5V

02/21/03

Related parts for PI6CV857

PI6CV857 Summary of contents

Page 1

... PWRDWN input is low. The PLL in the PI6CV857 clock driver uses input clocks (CLK, CLK) and feedback clocks (FBIN,FBIN) to provide high-performance, low- skew, low-jitter output differential clocks (Y[0:9], Y[0:9]). PI6CV857 is also able to track Spread Spectrum Clocking for reduced EMI ...

Page 2

... X Notes: For testing and power saving purposes, PI6CV857 will power down if the frequency of the reference inputs CLK, CLK is well below the operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CV857 will be powered down when the CLK,CLK stop running. ...

Page 3

... – – ± PI6CV857 µ PS8464D 02/21/03 ...

Page 4

... – – – PI6CV857 ° PS8464D 02/21/03 ...

Page 5

... – PI6CV857 – ± µ µ µ ...

Page 6

... PI6CV857 ...

Page 7

... DDQ / CLK R=60 R=60 V CLK PI6CV857 Figure 1. Output Load 14pF –V DDQ / 14pF –V DDQ /2 Figure 2. Output Load Test Circuit 7 PI6CV857 PLL Clock Driver for 2.5V DDR-SDRAM Memory GND GND SCOPE PS8464D 02/21/03 ...

Page 8

... C K FBIN FBIN Yx Yx Yx, FBOUT Yx, FBOUT t t cycle n cycle n jit(cc) cycle n cycle n+1 Figure 3. Cycle-to-Cycle Jitter large number of samples) Figure 4. Static Phase Offset t sk(o) Figure 5. Output Skew 8 PI6CV857 PLL Clock Driver for 2.5V DDR-SDRAM Memory t n PS8464D 02/21/03 ...

Page 9

... Figure 6. Period Jitter t half period jit(hper) half period n Figure 7. Half-Period Jitter sl(i), sl(o) sl(i), Figure 8. Input and Output Slew Rates 9 PLL Clock Driver for 2.5V DDR-SDRAM Memory n+1 half period 1 2 sl(o) PS8464D PI6CV857 02/21/03 ...

Page 10

... BSC 0.50 0.17 0. Pericom Semiconductor Corporation 1 0 PLL Clock Driver for 2.5V DDR-SDRAM Memory .236 6.0 .244 6.2 SEATING PLANE 0.45 .018 0.75 .030 .002 .006 .319 0.05 BSC 8.1 0.15 PI6CV857 0.09 .004 0.20 .008 PS8464D 02/21/03 ...

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