CY7C65620 Cypress Semiconductor Corporation., CY7C65620 Datasheet - Page 3

• Manufacturer Part Number: CY7C65620
• Description: Low-power Usb 2.0 Hub Controller Family
• Manufacturer: Cypress Semiconductor Corporation.

Introduction
EZ-USB HX2LP™ is Cypress’ next generation family of high
performance, low power USB 2.0 hub controllers. HX2LP is an
ultra low power single chip USB 2.0 hub controller with integrated
upstream and downstream transceivers, a USB Serial Interface
Engine (SIE), USB Hub Control and Repeater logic, and Trans-
action Translator (TT) logic. Cypress has also integrated many
of the external passive components, such as pull up and pull
down resistors, reducing the overall bill of materials required to
implement a hub design. The HX2LP portfolio consists of:
All device options are supported by Cypress’ world class
reference design kits, which include board schematics, bill of
materials, Gerber files, Orcad files, and thorough design
documentation.
USB Serial Interface Engine
The Serial Interface Engine (SIE) allows the CY7C656xx to
communicate with the USB host. The SIE handles the following
USB activity independently of the Hub Control Block.
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Hub Repeater
The Hub Repeater manages the connectivity between upstream
and downstream facing ports that are operating at the same
speed. It supports full-/low-speed connectivity and high-speed
connectivity. According to the USB 2.0 specification, the HUB
Repeater provides the following functions:
Transaction Translator
The Transaction Translator (TT) basically translates data from
one speed to another. A TT takes high-speed split transactions
and translates them to full-/low-speed transactions when the hub
is operating at high speed (the upstream port is connected to a
high-speed host controller) and has full-/low-speed devices
attached. The operating speed of a device attached on a
downstream facing port determines whether the Routing Logic
connects a port to the Transaction Translator or Hub Repeater.
If a full-/low-speed device is connected to the hub operating at
high speed, the data transfer route includes the Transaction
Translator. If a high-speed device is connected to this high-speed
Document #: 38-08037 Rev. *J
1. CY7C65630: 4-port/single transaction translator
2. CY7C65620:
• Sets up and tears down connectivity on packet boundaries
• Ensures orderly entry into and out of the Suspend state,
Bit stuffing/unstuffing
Checksum generation/checking
TOKEN type identification
Address checking.
This device option is for ultra low power applications that re-
quire four downstream ports. All four ports share a single
transaction translator. The CY7C65630 is available in a 56
QFN and is also pin-for-pin compatible with the CY7C65640.
This device option is for a 2-port bus powered application.
Both ports share a single transaction translator. The
CY7C65620 is available in a 56 QFN.
including proper handling of remote wakeups.
hub, the route only includes the repeater and no Transaction
Translator since the device and the hub are operating at the
same speed. When the hub is operating at full speed (the
upstream port is connected to a full-speed host controller), a
high-speed peripheral does not operate at its full capability.
These devices only work at full speed. Full- and low-speed
devices connected to this hub operate at their normal speed.
Applications
Typical applications for the HX2LP device family are:
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Functional Overview
The Cypress CY7C656xx USB 2.0 Hubs are high performance,
low system cost solutions for USB. The CY7C656xx USB 2.0
Hubs integrate 1.5 k
operation and all downstream 15 k
as series termination resistors on all upstream and downstream
D+ and D– pins. This results in optimization of system costs by
providing built-in support for the USB 2.0 specification.
System Initialization
On power up, the CY7C656xx reads an external SPI EEPROM
for configuration information. At the most basic level, this
EEPROM has the Vendor ID (VID), Product ID (PID), and Device
ID (DID) for the customer's application. For more specialized
applications, other configuration options can be specified. See
Configuration Options
After reading the EEPROM, if VBUSPOWER (connected to
up-stream V
on D+ to indicate its presence to the upstream hub, after which
a USB Bus Reset is expected. During this reset, CY7C656xx
initiates a chirp to indicate that it is a high-speed peripheral. In a
USB 2.0 system, the upstream hub responds with a chirp
sequence, and CY7C656xx is in a high-speed mode, with the
upstream D+ pull up resistor turned off. In USB 1.x systems, no
such chirp sequence from the upstream hub is seen, and
CY7C656xx operates as a normal 1.x hub (operating at full
speed).
Enumeration
After a USB Bus Reset, CY7C656xx is in an unaddressed,
unconfigured state (configuration value set to ’0’). During the
enumeration process, the host sets the hub's address and
configuration.
Once the hub is configured, the full hub functionality is available.
Standalone hubs
Motherboard hubs
Monitor hubs
Advanced port replicators
Docking stations
Split-PC designs
External personal storage drives
Keyboard hubs
BUS
) is high, CY7C656xx enables the pull up resistor
Ω
on page 12 for more details.
upstream pull up resistors for full-speed
Ω
pull down resistors as well
CY7C656xx
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