CYWUSB6935 Cypress Semiconductor Corporation., CYWUSB6935 Datasheet - Page 12

• Manufacturer Part Number: CYWUSB6935
• Description: Lr 2.4-ghz Dsss Radio Soc
• Manufacturer: Cypress Semiconductor Corporation.

Note:
Document #: 38-16008 Rev. *D
Bit
7
6
5
4
3
2
1
0
3.
All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The
status bits are affected by TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These
registers are read-only.
Valid B
Name
Valid B
Flow Violation B The Flow Violation B bit is used to signal whether an overflow or underflow condition has occurred for the Receive
EOF B
Full B
Valid A
Flow Violation A The Flow Violation A bit is used to signal whether an overflow or underflow condition has occurred for the Receive
EOF A
Full A
7
Addr: 0x08
Flow Violation
Description
The Valid B bit is true when all the bits in the Receive SERDES Data B register (Reg 0x0B) are valid.
When data is written into the Receive SERDES Data B register (Reg 0x0B) this bit is set if all of the bits within the byte
that has been written are valid. This bit cannot generate an interrupt.
SERDES Data B register (Reg 0x0B).
Overflow conditions occur when the radio loads new data into the Receive SERDES Data B register (Reg 0x0B) before
the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data B register (Reg
0x0B) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08)
The End of Frame B bit is used to signal whether an EOF event has occurred on the Channel B receive.
An EOF condition occurs for the Channel B Receiver when receive has begun and then the number of bit times specified
in the SERDES Control register (Reg 0x06) elapse without any valid bits being received. This bit is cleared by reading
the Receive Interrupt Status register (Reg 0x08)
The Full B bit is used to signal when the Receive SERDES Data B register (Reg 0x0B) is filled with data.
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B register
(Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete
byte has been received.
The Valid A bit is true when all of the bits in the Receive SERDES Data A Register (Reg 0x09) are valid.
When data is written into the Receive SERDES Data A register (Reg 0x09) this bit is set if all of the bits within the byte
that has been written are valid. This bit cannot generate an interrupt.
SERDES Data A register (Reg 0x09).
Overflow conditions occur when the radio loads new data into the Receive SERDES Data A register (Reg 0x09) before
the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data A register (Reg
0x09) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08)
The End of Frame A bit is used to signal whether an EOF event has occurred on the Channel A receive.
An EOF condition occurs for the Channel A Receiver when receive has begun and then the number of bit times specified
in the SERDES Control register (0x06) elapse without any valid bits being received. This bit is cleared by reading the
Receive Interrupt Status register (Reg 0x08).
The Full A bit is used to signal when the Receive SERDES Data A register (Reg 0x09) is filled with data.
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A
Register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or not
a complete byte has been received.
1 = Overflow/underflow interrupt pending for Receive SERDES Data B
0 = No overflow/underflow interrupt pending for Receive SERDES Data B
1 = Overflow/underflow interrupt pending for Receive SERDES Data A
0 = No overflow/underflow interrupt pending for Receive SERDES Data A
B
6
1 = All bits are valid for Receive SERDES Data B
0 = Not all bits are valid for Receive SERDES Data B
1 = EOF interrupt pending for Channel B
0 = No EOF interrupt pending for Channel B
1 = Receive SERDES Data B full interrupt pending
0 = No Receive SERDES Data B full interrupt pending
1 = All bits are valid for Receive SERDES Data A
0 = Not all bits are valid for Receive SERDES Data A
1 = EOF interrupt pending for Channel A
0 = No EOF interrupt pending for Channel A
1 = Receive SERDES Data A full interrupt pending
0 = No Receive SERDES Data A full interrupt pending
EOF B
Figure 7-7. Receive SERDES Interrupt Status
5
REG_RX_INT_STAT
Full B
4
Valid A
3
Flow Violation
[3]
A
2
EOF A
1
CYWUSB6935
Default: 0x00
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Full A
0
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