CAT24C05 Catalyst Semiconductor, CAT24C05 Datasheet
CAT24C05
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CAT24C05 Summary of contents
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... Write operations can be inhibited for upper half of memory by taking the WP pin High. External address pins make it possible to address up to eight CAT24C03 or four CAT24C05 devices on the same bus. FUNCTIONAL SYMBOL TSOT-23 (TD) SCL ...
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... V to +6.5 V Units Program/ Erase Cycles Years Min Max Units μ μ 0.4 V 0.2 V Max Units 200 150 μA 100 1 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice ...
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... PU CC A.C. TEST CONDITIONS Input Levels 0 Input Rise and Fall Times ≤ Input Reference Levels 0 Output Reference Levels 0 Output Load Current Source: I © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Standard Min 4 4.7 4 4.7 0 250 4 4.7 100 0 2 ...
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... The 3 address space extension bits are assigned as illustrated in Figure must match the state of the external address pins, 0 and a (CAT24C05) is internal address bit. 8 Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA th line during the 9 clock cycle (Figure 3) ...
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... SDA OUT © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice R/W CAT24C03 R/W CAT24C05 8 ACK DELAY (≤ HIGH LOW t HD:DAT t SU:DAT CAT24C03/05 STOP CONDITION BUS RELEASE DELAY (RECEIVER) 9 ACK SETUP (≥ t SU:DAT ) ...
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... If the WP pin is HIGH during the strobe interval, the CAT24C03/05 will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24C03/05 is shipped erased, i.e., all bytes are FFh. © 2006 by Catalyst Semiconductor, Inc. 6 Characteristics subject to change without notice ...
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... Figure 7. Page Write Sequence S BUS ACTIVITY SLAVE R MASTER ADDRESS T S SLAVE ≤ 15 Figure 8. WP Timing ADDRESS 1 SCL a 7 SDA WP © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice S T ADDRESS A SLAVE BYTE R ADDRESS ÷ ACK t WR ...
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... Master responds with a NoACK, followed by a STOP (Figure 11). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap-around at end of memory (rather than end of page). Doc. No. 1116, Rev. B © 2006 by Catalyst Semiconductor, Inc. 8 Characteristics subject to change without notice ...
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... Figure 10. Selective Read Sequence S BUS ACTIVITY MASTER ADDRESS T S SLAVE Figure 11. Sequential Read Sequence BUS ACTIVITY: SLAVE MASTER ADDRESS A SLAVE C K © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice SLAVE R ADDRESS DATA SLAVE C BYTE Bit DATA OUT ...
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... L 0.115 0.130 Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 Doc. No. 1116, Rev MAX 4.57 3.81 0.56 1.77 10.16 8.25 7.11 9.65 0.150 24C16_8-LEAD_DIP_(300P).eps © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice ...
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... For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012 dimensions. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice θ1 A1 NOM MAX 0 ...
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... For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-153. Doc. No. 1116, Rev θ MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00 12 SEE DETAIL A c GAGE PLANE 0.25 L SEATING PLANE SEE DETAIL A © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice ...
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... E 2.90 3.00 E2 1.20 1.30 e 0.50 TYP L 0.20 0.30 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-229. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice A3 MAX 0.80 0.05 E2 0.65 0.30 2.10 1.50 3.10 1.40 0. CAT24C03/05 ...
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... Complies with JEDEC specification MO-193. Doc. No. 1116, Rev MIN NOM MAX A — — 1.0 A1 0.01 0.05 0.1 A2 0.80 0.87 0.9 b 0.30 — 0.45 c 0.12 0.15 0.20 D 2.90 BSC E 2.80 BSC E1 1.60 BSC e 0.95 BSC e1 1.90 BSC L 0.30 0.40 0.50 L1 0.60 REF L2 0.25 BSC θ 0° 8° 14 GAUGE PLANE L2 θ © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice ...
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... I = Temperature Range WW = Production Week F = Lead Finish 4 = NiPdAu 3 = Matte-Tin Note: (1) The circle on the package marking indicates the location of Pin 1. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8-Lead SOIC 24CXXWI FYYWWR CSI = Catalyst Semiconductor, Inc Device Code (see Marking Code table below) ...
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... Rev 24C05 Rev Production Year Production Month M = Production Month 16 XXYM Matte-Tin NiPdAu Matte-Tin NiPdAu 24C01 24C02 24C04 RC MP 24C08 RD MR 24C16 Production Year © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice ...
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... The standard lead finish is NiPdAu pre-plated (PPF) lead frames. (3) The device used in the above example is a CAT24C03YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel). (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. © 2006 by Catalyst Semiconductor, Inc. ...
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... Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Comments CAT24CAT03 Data Sheet initial issue CAT24CAT05 Data Sheet initial issue Combine CAT24C03 and CAT24C05 data sheets into one data sheet. Update marking and ordering information. Update Package Marking Publication #: 1116 Revison: B Issue date: ...