AP89341 Aplus Integrated circuits Inc., AP89341 Datasheet
AP89341
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AP89341 Summary of contents
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... Integrated Circuits Inc. VOICE OTP IC aP89341 – 341sec aP89170 – 170sec aP89085 – 85sec A PLUS INTEGRATED CIRCUITS INC. Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115)台北市南港區成功路一段 32 號 3 樓之 10. ...
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... Development System support voice compilation. DESCRIPTION aP89341/170/085 series high performance Voice OTP is fabricated with Standard CMOS process with embedded 8M/4M/2M bits EPROM. It can store up to 341/170/85 sec voice message with 4-bit ADPCM compression at 6KHz sampling rate. 8-bit PCM is also available as user selectable option. ...
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... Programmable output (I/O pin) DCLK Reset pin (input pin with internal pull-down) PGM Trigger pin (I/O pin with internal pull-down) M1 Mode select pin 1 (input with internal pull-down) M0 Mode select pin 0 (input with internal pull-down) IO0~IO6 Trigger input (I/O pin with internal pull-down) 2 aP89341/170/085 Aug 17, 2007 ...
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... BUSYB, 8K, 4K, 2K, 1K, 16Hz, 1M and EMPTY (or FULLB). - During OTP programming, OUT1 serves as OEB while OUT2 serves as SIO (serial data IO). COUT Analog 8-bit current mode D/A output for voice playback RST Chip reset in playback mode or DCLK pin in OTP programming mode. Ver 3.0 aP89341/170/085 3 Aug 17, 2007 ...
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... Voice files created by the PC base developing system are stored in the built-in EPROM of the aP89341/170/085 chip as a number of fixed length Voice Blocks. Voice Blocks are then selected and grouped into Voice Groups for playback 254 Voice Groups are allowed. A Voice Block Table is used to store the information of combinations of Voice Blocks and then group them together to form Voice Group ...
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... Note: BUSY can be set or reset associated with each Voice Block. Stop plus must be set to enable in order to have STOP plus to come out at the end of playback. Ver 3.0 Fig.2 Ramp-up-down Disable OUT1 OUT2 LED1 LED2 STOP LED1 LED1 BUSY LED1 BUSY Fig. 3 Output waveforms 5 aP89341/170/085 OUT3 BUSY LED2 STOP BUSYB Aug 17, 2007 ...
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... Stop pulse disable or enable Fig Fig. 9 show the voice playback with different combination of triggering mode and the relationship between outputs and voice playback. Fig. 4 Level, Unholdable, Non-retriggerable Fig. 6 SBT sequential trigger with Level Holdable and Unholdable Ver 3.0 aP89341/170/085 Fig. 5 Level Holdable 6 Aug 17, 2007 ...
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... Integrated Circuits Inc. Fig. 9 SBT sequential trigger with Edge Holdable and Unholdable TRIGGER MODES There are three trigger modes available for aP89341/170/085 series which are determined by setting M1 and M2 pins to logic HIGH or LOW. Key Trigger Mode (M1=0; M0=0); CPU Parallel Trigger Mode (M1=0; M0=1); CPU Serial Command Mode (M1=1; M0=0); ...
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... HIGH HIGH HIGH NC HIGH HIGH HIGH HIGH HIGH HIGH NC HIGH HIGH NC NC HIGH HIGH aP89341/170/085 HIGH HIGH HIGH ...
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... S[8:1] = 1111 1101 (FD hex) for Voice Group #254 CPU Serial Command Mode (M1=1, M0=0) This trigger mode is specially designed for simple CPU interface. The aP89341/170/085 is controlled by command sent to it from the host CPU are used to input command word into the chip while OUT1 to OUT3 as output from the chip to the host CPU for feedback response. ...
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... Fig. 11 Power-up command timing 10 aP89341/170/085 Description for VOUT direct drive) COUT transistor drive) Power down the chip with NO ramp-down (suitable for VOUT direct drive) Power down the chip WITH ramp-down (suitable for COUT transistor drive) Set output status for OUT2 pin ...
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... BUSYB is the logical inversion of BUSY. 4. EMPTY (or FULLB) is the logical inversion of FULL. 5. Only the 1MHz clock will not be stopped by the PAUSE command. Ver 3.0 Fig. 12 Power-down commands timing OUT2 G[3:0] BUSYB 100 8KHz 101 4KHz 110 2KHz 111 11 aP89341/170/085 OUT2 1KHz 16Hz 1MHz FULLB Aug 17, 2007 ...
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... The FULL signal will become logic LOW once the Voice Group is played and the address buffer is released and ready for next PREFECT action. 5. Using the PREFECT make sure there is no gap between each Voice Group. Ver 3.0 Fig. 16 Prefetch next Voice Group timing 12 aP89341/170/085 Aug 17, 2007 ...
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... Integrated Circuits Inc. BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol 0.3< OUT T (Operating): T (Junction) T (Storage) Ver 3.0 Fig. 17 Block Diagram Rating -0.5 ~ +3.8 < <V <V SS OUT DD -40 ~ +85 -40 ~ +125 -55 ~ +125 13 aP89341/170/085 Unit ℃ ℃ ℃ Aug 17, 2007 ...
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... O/P low Current Frequency Stability F/F Ver 3 70℃ 3.3V Min. Typ. Max. 2.2 3.0 3 2.5 3.0 3.5 -0.3 0 0.5 120 - aP89341/170/085 = Unit Condition V μA I/O open mA I/O open =3. =3.0V mA Vout=0.3V mA Vout=2. COUT =1. =2. =0.3V Fosc(2.7V) - Fosc(3.4V) Fosc(3V) % Aug 17, 2007 ...
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... S1~S8, SBT COUT STOP BUSY CPU Parallel Mode t AS Addr. S1~S8 SBT t SBTW CPU Serial Command Mode t CS S1(CS S3(DI) S2(SCK COUT BUSY FULL Ver 3 SCKW t SCKC Fig. 18 Timing Waveform 15 aP89341/170/085 t STPD t STPW COUTD Aug 17, 2007 t BH ...
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... This parameter is proportional to the sampling frequency. Ver 3 70℃ 3.3V Min. Typ 200 100 100 100 16 65 100 100 100 100 1 2 100 16 aP89341/170/085 = 0V, 8KHz sampling ) SS Max. Unit ms ms μs μs μs 256 64 ms 100 μ μs μs μ ...
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... Note: The data in the above tables are within 3% accuracy and measured at V subjected to IC lot to lot variation. Ver 3.0 R OSC KOhm 300 290 280 270 260 250 240 230 220 210 200 190 180 170 160 150 17 aP89341/170/085 Sampling Frequency R OSC KOhm KHz 140 11.00 130 11.76 120 12.50 110 13.33 100 14.51 91 15.63 82 16.95 75 18. ...
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... Fig. 22 Using 3.3V Battery 0.01uF VDD, AVDD,VPP RST R OSC COUT OSC • • VOUT1 • • • • VOUT2 S8 OUT1 SBT VSS, AVSS Fig. 23 Using 4.5V Battery 18 aP89341/170/085 C 8Ω 1/4W Speaker 16Ω Speaker C 8Ω 1/4 Speaker 16Ω Speaker Aug 17, 2007 ...
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... Reference value for the above components are C = 2.2uF 390 Ohm and T = 8050D. 5. Refer to the Oscillator Resistor Table for suitable value of Rosc. Ver 3.0 0.01uF R OSC VDD, AVDD,VPP RST OSC COUT • • • • • • S8 Rin 3 OUT[1..3] VSS, Fig CPU Control with COUT 19 aP89341/170/085 C 8Ω 1/4W Speaker T Rb Aug 17, 2007 ...
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... BUSY FULL Rin = 860KΩ x (VIN-VOUT) / VIN Fig CPU Control with TDA Power Amplifier Ver 3.0 VDD, AVDD,VPP RST 10uF OSC COUT S1 (CS) S2 (SCK) 33Ω S3 (DI) OUT1 OUT3 VSS, AVSS 20 aP89341/170/085 10uF 2 Vcc 10KΩ 10u Gnd 0.01uF 4 4.7Ω ...
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... Notes: 1. Two VPP pads should be connected to the Positive Power Supply during voice playback. 2. VDD and AVDD should be connected to the Positive Power Supply. 3. VSS and AVSS should be connected to the Power GND. 4. Substrate should be connected to the Power GND. Ver 3.0 aP89341 21 aP89341/170/085 Aug 17, 2007 ...
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... VPP and VSL pads should be connected to the Positive Power Supply during voice playback. 6. VDD and AVDD should be connected to the Positive Power Supply. 7. VSS and AVSS should be connected to the Power GND. 8. Substrate should be connected to the Power GND. Ver 3.0 aP89341/170/085 aP8917 aP8908 22 Aug 17, 2007 ...
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... Integrated Circuits Inc. PACKAGES DIMENSION OUTLINES 24-Pin 300mil P-DIP Package 28-Pin 300mil SOP Package Ver 3.0 aP89341/170/085 23 Aug 17, 2007 ...