STPMC1 ST Microelectronics, STPMC1 Datasheet - Page 60

• Manufacturer Part Number: STPMC1
• Description: Programmable poly-phase energy calculator IC
• Manufacturer: ST Microelectronics

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Theory of operation
9.21.2
Figure 21. Timing for data records reading
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SCS
SCS
SYN
SYN
SCLNLC
SCLNLC
SDATD
SDATD
Reading data records
Data record reading takes place most often when there is an on-board microcontroller in an
application. This microcontroller is capable of reading all measurement results and all
system signals (configuration, calibration, status, mode). Again, the time step can be as
short as 30 ns. There are two phases of reading, called latching and shifting .
Latching is used to sample results into transmission latches. The transmission latches are
the flip-flops that hold the data in the SPI interface. This is done with the active pulse on
SYN when SCS is idle. The length of pulse on SYN must be longer than 2 periods of
measurement clock, i.e. more than 500 ns at 4 MHz.
The shifting starts when SCS become active. In the beginning of this phase another, but
much shorter, pulse (30 ns) on SYN should be applied in order to ensure that an internal
transmission serial clock counter is reset to zero. An alternative way is to extend the pulse
on SYN into the second phase of reading. After that reset is done, a 32 serial clocks per
data record should be applied. Up to 8 data records can be read this way. This procedure
can be aborted at any time by deactivation of SCS .
The timing diagram of the reading operation is shown in timing for data records reading. One
can see the latching and beginning of shifting phase of the first byte of the first data record
and end of reading.
t
t
t
t
t
t
t
1
2
3
4
5
7
8
: Internal data transferred to SDATD
: SDATD data is stable and can be read
t
t
−>
−>
−>
−>
−>
1
1
t
t
t
t
t
2
3
4
5
6
: Data latched, SPI idle. Interval value > 30 ns.
: SPI reset and enabled for read operation. Interval value > 30 ns
t
t
: Latching Phase. Interval value > 2/f
: Enable SPI for read operation. Interval value > 30 ns.
: Serial clock counter is reset. Interval value > 30 ns.
2
2
t
t
3
3
t
t
4
4
t
t
5
5
t
t
6
6
Doc ID 15728 Rev 1
t
t
7
7
t
t
8
8
CLK
1st byte
1st byte
f(read)
f(read)
last bit of 32nd byte
last bit of 32nd byte
STPMC1