FM24W256 Ramtron, FM24W256 Datasheet
FM24W256
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FM24W256 Summary of contents
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... EEPROM. These capabilities make the FM24W256 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss ...
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... SCL Input WP Input VDD Supply VSS Supply Rev. 1.3 July 2011 FM24W256 - 256Kb Wide Voltage I2C F-RAM Address Counter Latch Serial to Parallel Converter Control Logic Figure 1. Block Diagram Pin Description Device Select Address 0-2: These pins are used to select one devices of the same type on the same two-wire bus ...
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... This is explained in more detail in the interface section below. Users expect several obvious system benefits from the FM24W256 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example ...
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... Slave Address The first byte that the FM24W256 expects after a start condition is the slave address. As shown in Figure 4, the slave address contains the device type, the device select address bits, and a bit that specifies if the transaction is a read or a write ...
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... After the address information has been transmitted, data transfer between the bus master and the FM24W256 can begin. For a read operation the FM24W256 will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM24W256 will transfer the next sequential byte ...
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... Figure 6. Multiple Byte Write There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24W256 attempts to read out additional data onto the bus. The four valid methods are: 1. The bus master issues a no-acknowledge in the 9 This is illustrated in the diagrams below ...
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... Address Acknowledge Slave Address 1 A Data Byte Acknowledge Figure 8. Sequential Read Address Address MSB A Address LSB Acknowledge Figure 9. Selective (Random) Read FM24W256 - 256Kb Wide Voltage I2C F-RAM No Acknowledge Stop 1 P Data No Acknowledge Stop A Data Byte 1 P Data Acknowledge Start Address ...
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... IH -0.3V and V , other inputs Stop command issued Does not apply to WP, A2-A0 pins FM24W256 - 256Kb Wide Voltage I2C F-RAM Ratings -1.0V to +7.0V -1.0V to +7.0V and V < V +1. -55C to +125C 260 C 3.5kV 1.25kV 200V MSL-1 (SOIC) MSL-2 (EIAJ) ...
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... Max Units min -40 +85 2.7V to 5.5V unless otherwise specified min) to First Access (Start condition) DD min) DD waveform. DD FM24W256 - 256Kb Wide Voltage I2C F-RAM Min Max Min Max Units 0 400 0 1000 kHz s 1.3 0.6 s 0.6 0.4 s 0.9 0.55 s 1.3 0.5 ...
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... Read Bus Timing SCL t SU:SDA SDA Start Write Bus Timing SCL SDA Data Retention Symbol Parameter T +85º +80ºC @ +75ºC @ Rev. 1.3 July 2011 FM24W256 - 256Kb Wide Voltage I2C F-RAM HIGH BUF t AA Stop Start t HD:STA ...
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... Legend: XXXXXX= part number, P= package type (G=SOIC, EG=EIAJ SOIC) R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24W256, “Green” SOIC package, Year 2010, Work Week 37 FM24W256-G A00002G1 RIC1037 Recommended PCB Footprint 7.70 3.70 2.00 0.65 1.27 0.25 0.50 0. ...
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... Legend: XXXXXX= part number, P= package type (G=SOIC, EG=EIAJ SOIC) R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24W256, “Green” EIAJ SOIC package, Year 2010, Work Week 37 FM24W256-EG A00002G1 RIC1037 Recommended PCB Footprint 9.30 5.00 2.15 0.65 1.27 0.19 0.25 0- 8 ...
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... Rev. 1.3 July 2011 Date Summary Initial Release Added ESD ratings. Changed V Changed to MSL-2 for EIAJ package. Changed t EIAJ package is Not Recommended for New Designs (NRND). FM24W256 - 256Kb Wide Voltage I2C F-RAM (max +0.3V and t spec limits Page ...