T7256 Agere Systems, T7256 Datasheet - Page 56

• Manufacturer Part Number: T7256
• Description: (T7234 - T7256) Compliance
• Manufacturer: Agere Systems

T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Glossary
ERC1:
ESD:
ETSI:
FEBE:
FSC[2:0]:
FSP:
FT:
FTE/TDMDI:
GIR0:
GND
GND
GR0:
GR1:
GR2:
HBM:
HDLC:
HIGHZ:
HN:
HP:
I4C:
I4CM:
I4I:
ILINT:
ILINTM:
52
A
O
:
:
(continued)
eoc state machine control—
information register.
Electrostatic discharge.
European Telecommunications
Standards Institute.
Far-end block error (register
CFR1, bit 5).
Frame strobe (FS) control,
(register TDR0, bits 2—0).
Frame strobe (FS) polarity
(register TDR0, bit 3).
Fixed/adaptive timing control
(register GR2, bit 0).
Fixed/adaptive timing mode
select.
Global interrupt register.
Analog ground.
Crystal oscillator ground.
Global device control—device
configuration register.
Global device control—
U-interface register.
Global device control—
S/T-interface register.
Human-body model.
High-level data link control.
High-impedance control.
Hybrid negative input for
U-interface.
Hybrid positive input for
U-interface.
INFO 4 change (register SIR0,
bit 3).
INFO 4 change mask (register
SIR1, bit 3).
INFO 4 indicator (register CFR1,
bit 7).
Insertion loss interrupt
(register MIR0, bit 1).
Insertion loss interrupt mask
(register MIR1, bit 1).
ILOSS:
ILOSS:
ISDN:
ITU-T:
I[8:1]R:
I[8:1]T:
LON:
LOP:
LPBK:
MCR0:
MCR1:
MCR2:
MCR3:
MCR4:
MCR5:
MINT:
MIR0:
MIR1:
MLT:
MULTIF:
NEBE:
NTM:
OOF:
OPTOIN:
OUSC:
Insertion loss test control
(register CFR0, bit 0).
Insertion loss test control.
Integrated services digital net-
work.
International Telecommunication
Union-Telecommunication Sec-
tor.
Receive eoc information
(register ECR3, bits 0—7).
Transmit eoc information
(register ERC1, bits 0—7).
Line driver negative output for
U-interface.
Line driver positive output for
U-interface.
U-interface analog loopback
(register GR1, bit 0).
Q-channel bits register.
S subchannel 1 register.
S subchannel 2 register.
S subchannel 3 register.
S subchannel 4 register.
S subchannel 5 register.
Maintenance interrupt
(register GIR0, bit 2).
Maintenance interrupt register.
Maintenance interrupt mask
register.
Metallic loop termination.
Multiframing control (register
GR0, bit 5).
Near-end block error (register
CFR1, bit 4).
NT test mode (register GR1, bit 3).
Out of frame (register CFR1,
bit 2).
Optoisolator input.
Other U-interface state change
(register UIR0, bit 3).
Lucent Technologies Inc.
February 1998