MB15C03 Fujitsu, MB15C03 Datasheet - Page 11

• Manufacturer Part Number: MB15C03
• Description: Single Serial Input PLL Frequency Synthesizer On-Chip prescaler
• Manufacturer: Fujitsu

3. Setting the Divide Ratio
(1) Serial data format
The format of the serial data is shown is Figure 3. The serial data is composed of control bits and divide ratio
setting data. The contorl bits select the programmable divider or programmable reference divider.
In case of the programmable divider, serial data consists of 18 bits (6 bits for the swallow counter and 12 bits
for the programmable counter) and control bits as shown in Figure 3.1. In case of the programmable reference
divider, the serial data consists of 14 bits and 2 control bits as shown in Figure 3.2.
The control bits are set to:
(2) The flow of serial data
Serial data is received via data pin in synchronization with the clock input and loaded into shift register which
contains the divide ratio setting data and into the control register which contains the control bit. The logical
product (through the AND gate in Figure 4) of LE and the control register output (i.e., control bit) is fed to the
enable input of the latches. Accordingly, when LE is set high, the latch for the divider identitied by the control bit
is enabled and the divide ratio data from the shift register is loaded into the selected counter(s).
Control bit
(=0) (=0)
C
0
C
1
Control bit
LSB
(=0) (=1)
A
C
0
0
A
C
1
1
Figure 3.2 Divide ratio for the programmable reference divider
Swallow counter
LSB
A
R
2
0
Figure 3.1 Divide ratio for the programmable divider
A
R
3
1
C0 = C1= 0
C0 = 0, C1 = 1
A
R
4
2
Figure 3 Serial data format
A
R
5
3
Programmable reference counter
Direction of data input
Direction of data input
N
R
0
4
for the programmable divider
for the programmable reference divider.
N
R
1
5
N
R
2
6
Programmable counter
N
R
3
7
N
R
4
8
N
R
5
9
10
N
R
6
11
R
N
7
12
N
R
8
MB15C03
MSB
13
N
R
9
10
N
MSB
11
N
11