MB86330 Fujitsu Media Devices Limited, MB86330 Datasheet - Page 15

• Manufacturer Part Number: MB86330
• Description: 16-bit Fixed-point DSP
• Manufacturer: Fujitsu Media Devices Limited

The DSP splits the contents of processing in one cycle to increase the number of pipeline sectors for high-speed
operation. For operations using product adders such as product addition and multiplication, and for operations
using 40-bit adders such as 40-bit addition, the processing latency is two cycles.
PRODUCT ADDITION
For product addition and multiplication, the latency is two cycles. Because it is provided with a dual product
adder (MAC) for alternate processing every cycle, however, the DSP can process n successive product addition
(multiplication) steps in (n + 1) cycles.
BASIC PIPELINE OPERATION
Pipeline phase
Operation (latency 1)
Operation (latency 2)
Transfer (Reg-Reg R/W)
Transfer (Mem Read)
Transfer (Mem Write)
Operation latency 2
MSM (1)
PC
PC
PC
PC
PC
PC
MSM (2)
dec1
dec1
dec1
dec1
dec1
DE1
MSM (3)
dec2
dec2
dec2
dec2
dec2
DE2
adr
adr
adr
adr
adr
MSM (4)
(n + 1) cycles
ALU1
R/W
[adr]
EX1
R
ALU2
EX2
W
MSM (n - 1)
dec1: 1st. decoding
dec2: 2nd. decoding
adr:
[adr]
ALU:
R:
W:
PC: Program fetch cycle
DE1: Decode 1st. cycle
DE2: Decode 2nd. cycle
EX1: Execute 1st. cycle
EX2: Execute 2nd. cycle
MSM (n)
Address generation
Address maintenance
Operation
Reading
Writing
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MB86330
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