FMS9884A Fairchild Semiconductor, FMS9884A Datasheet
FMS9884A
Related parts for FMS9884A
FMS9884A Summary of contents
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... IN Clamp Clamp IN VREFIN CLAMP INVSCK XCK HSIN COAST LPF SDA SCL A Control PWRDN Product Number FMS9884AKAC100 FMS9884AKAC140 FMS9884AKAC175 RPD 7-0 A/D Gain & Converter Offset GPD 7-0 Gain & A/D Offset Converter BPD 7-0 Gain & A/D Converter Offset SCK ICLAMP Timing Generator HS DCK DCK ...
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... PRODUCT SPECIFICATION Architectural Overview Conversion Channels ICLAMP Figure 1. Clamping to the back-porch Gain and Offset A/D Converter 2 Output Data Configuration Timing and Control Timing Generator Phase Locked Loop Serial Interface FMS9884A REV. 1.2.2 12/7/01 ...
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... FMS9884A Pin Assignments (128-Lead MQFP (KA) Package) GND 103 VDDO 104 DRA7 105 DRA6 106 DRA5 107 DRA4 108 DRA3 109 DRA2 110 DRA1 111 DRA0 112 GND 113 VDDO 114 DCK 115 DCK 116 HSOUT 117 DCSOUT 118 GND 119 VDDO ...
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... DBB 90 DGA 4 2 DBB 91 DGA 3 1 DBB 92 DGA 2 0 DBB 93 GND 1 DBB DDO GND 95 DRB DRB DDO 6 FMS9884A No. Name 97 DRB 5 98 DRB 4 99 DRB 3 100 DRB 2 101 DRB 1 102 DRB 0 103 GND 104 V DDO 105 DRA 7 106 DRA 6 107 ...
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... Output Data Clock Inverted. Inverted clock for strobing output data to external logic. Horizontal Sync Output. Reconstructed HSYNC delayed by FMS9884A latency and synchronized with DCK. Leading edge is synchronized to start of data output. Polarity is always active HIGH. Horizontal Sync input. Schmitt trigger threshold is 1.5V source should be clamped at 3 ...
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... PLLN 3–0 stored in the six upper 5-0 OSR X X 5–0 stored in the six upper 5-0 OSG X X 5–0 stored in the six upper 5-0 OSB X X 5–0 FMS9884A Default (hex) 69 (1693) D0 (1693 REV. 1.2.2 12/7/01 ...
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... FMS9884A Name Address Function PHASE 0B Sampling clock phase. PHASE 7-0 register bits 7-3. PHASE sets the sampling clock phase in 11.25° increments. Default value is decimal 16. PLLCTRL 0C PLL Control CONFIG2 0D Configuration 0E Reserved 0F Reserved Register Definitions Configuration Register 1 (0A) Bit no. Name Type 0 1 XCKSEL R/W 2 XCLAMPOL ...
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... Odd samples to Port A, even samples to Port B. Reserved. Set to 00. Description Reserved. After power-up, initialize this register with the default value 0x00. Register 0F does not respond with an acknowledge during serial bus access. Consequently, ACK remains H instead of being pulled H. Clamps FMS9884A Ω REV. 1.2.2 12/7/01 Ω ...
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... FMS9884A Analog-to-Digital Converter Table 1. Gain Calibration G Conversion Range (mV) 7 1000 h • G Gain 7-0 Register OS Offset 5-0 Register REV. 1.2.2 12/7/01 Table 2. Offset Calibration OS 5-0 500 0 700 Sampling Clock PHASE Adjustment ⁄ V REF D Current BIAS OFFSET D/A A/D Core RGB IN Track & + Hold V OS ...
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... Zones of Uncertainty SCK D 7-0 Figure 4. Ideal Pixel Sampling 10 PHASE RGBn Figure 3. Internal Sampling Clock, SCK Timing SCK D 7 SCK D 7-0 Voltage References Zones of Serendipity Figure 5. Acceptable Pixel Sampling Zones of Uncertainty Figure 6. Improper Pixel Sampling REV. 1.2.2 12/7/01 FMS9884A ...
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... FMS9884A Digital Data Outputs HSIN PXCK/XCK SC K RGBIN S0 DCK DCK D[7..0] HSOUT REV. 1.2.2 12/7/01 PHASE Figure 7. Output Timing Alternate Pixel Sampling Mode PRODUCT SPECIFICATION ...
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... REV. 1.2.2 12/7/01 FMS9884A ...
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... FMS9884A RGBIN HSIN PXCK HS 5 PIPE DELAY SCK DATACK DA 7-0 HSOUT Figure 14. Single Port Mode, Alternate Pixel Sampling, (Even Pixels) RGBIN HSIN PXCK HS 5.5 PIPE DELAY SCK DATACK DA 7-0 HSOUT Figure 15. Single Port Mode, Alternate Pixel Sampling, (Odd Pixels) ...
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... RGBIN HSIN PXCK HS 5.5 PIPE DELAY SCK DATACK DA 7-0 DB 7-0 HSOUT Figure 19. Dual Port Mode, Interleaved Outputs, Alternate Pixel Sampling, (Odd Pixels Figure 17. Dual Port Mode, Parallel Outputs REV. 1.2.2 12/7/01 FMS9884A ...
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... FMS9884A RGBIN HSIN PXCK HS 6 PIPE DELAY SCK DATACK DA 7-0 DB 7-0 HSOUT Figure 20. Dual Port Mode, Parallel Outputs, Alternate Pixel Sampling, (Even Pixels RGBIN HSIN PXCK HS SCK DATACK DA 7-0 DB 7-0 HSOUT Figure 21. Dual Port Mode, Parallel Outputs, Alternate Pixel Sampling, (Odd Pixels) ...
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... MHz 85 Hz 91.1 kHz 157.500 MHz 60 Hz 75.0 kHz 162.000 MHz 65 Hz 81.3 kHz 175.500 MHz 70 Hz 87.5 kHz 189.000 MHz 93.8 kHz 202.500 MHz 106.3 kHz 229.500 MHz* VDDP LPF FMS9884A FVCO IPUMP 1-0 2-0 01 100 01 100 01 100 01 100 01 100 01 100 01 100 01 100 01 ...
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... FMS9884A Table 4. VCO Frequency Bands FVCO Frequency Range (MHz) KVCO (MHz/V) 2-0 00 20– 80–120 11 110–175 Table 5. Charge Pump Current Levels IPUMP Current (µA) 2-0 000 001 010 011 100 101 110 111 COAST HSIN COAST HSOUT REV. 1.2.2 12/7/ 100 50 100 ...
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... Table 6. Serial Interface Address Codes A 1 DSU t DAL t DAH Figure 24. Serial Bus: Read/Write Timing bit 5 bit 4 bit 3 Figure 25. SerialBus: Typical Byte Transfer 7-bit Address STASU STOSU bit 2 bit 1 bit 0 ACK A1 A0 R/W\ ACK REV. 1.2.2 12/7/01 FMS9884A Ω ...
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... FMS9884A Data Transfer via Serial Interface REV. 1.2.2 12/7/01 PRODUCT SPECIFICATION Serial Interface Read/Write Examples Write to one register Write to four consecutive registers Read from one register Read from four registers 19 ...
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... DDO T Ambient Temperature, Still Air A A/D analog input range, min. A/D analog input range, max Min. -0.5 2 -0.3 -5.0 2 -0.5 -10.0 2 -0.5 -6.0 -8.0 -65 Min. 3.0 ≤ 140 Ms/s 3.0 > 140 Ms/s 3.4 2.2 0 1000 FMS9884A Typ. Max. Unit DDA 5 DDA 10 6 second 150 °C 300 °C 220 °C 150 ° ...
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... FMS9884A Electrical Characteristics Parameter Power Supply Currents I Supply current, ADC DDA 2 I Supply current , Digital Output DDD I Supply current, PLL DDP P Power dissipation D I Power-down current PD P Powered-down disspation DD Digital Inputs/Outputs C Input Capacitance I C Output Capacitance O I Input Current, HIGH IH I Input Current, LOW ...
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... FMS9884A Min. Typ. Max 70°C 10 175 0 to 70°C -0.5 2 70°C 15 110 0 to 70°C 108 140 175 0 to 70° 70°C 4 70° ...
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... FMS9884A System Performance Characteristics Parameter Thermal θ Resistance, junction-to-case JC θ Resistance, junction-to-ambient JA Notes: 1. Calibrated to 700 mV input. 2. Percentage of Full Scale (uncalibrated Applications Information REV. 1.2.2 12/7/01 (continued) Conditions 100 120 140 Pixel Clock (MHz) Figure 27. Pixel Clock Jitter vs. Frequency ...
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... NC5 38 NC6 46 NC7 127 REFIN R9 10K 115 DATACK 116 DATACK 117 HSOUT 125 PWRDN 126 REFOUT C19 0. 1 µF FMS9884A VDDO 7..0] 65 BA7 ...
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... FMS9884A C1 .047µF J1 RED 1 GREEN 2 BLUE .047µ .047µ SVGA COAST PWRDN\ SDA SCL Figure 29. Schematic, VGA Digitizer, Dual Port Outputs Printed Wiring Board Design Guidelines Analog Inputs Ω REV. 1.2.2 12/7/01 ...
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... C16 C17 + C26 10 µF 0.1µF 0.1µF 0.1µF 0.1µF U3 RC1117-3.3 L3 BEAD 2 OUT 4 C22 C23 C24 OUT 0.1µF 0.1µF 0.1µF + C25 10µF Figure 31. Recommended Power Distribution FMS9884A 3 IN ADJ/GND C1 1 0.1µF 3 Power Input IN ADJ/GND 0.1µF 10µ ADJ/GND C9 1 0.1µF REV. 1.2.2 12/7/01 Ω ...
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... FMS9884A REV. 1.2.2 12/7/01 PRODUCT SPECIFICATION Firmware 27 ...
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... Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm in excess of the "b" dimension at the maximum material condition Datum Plane See Lead Detail Base Plane -C- LEAD COPLANARITY ccc C FMS9884A .40 Min. 0° Min. 0.13 R Min. .13/.30 R 0–7° L 1.60 Ref. Lead Detail REV. 1.2.2 12/7/01 ...
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... A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness. 2001 Fairchild Semiconductor Corporation FMS9884A Package Marking 9884AKAC100 9884AKAC140 9884AKAC175 12/7/01 0.0m 006 ...