CMX981 Consumer Microcircuits Limited, CMX981 Datasheet - Page 24

• Manufacturer Part Number: CMX981
• Description: Advanceddigital Radio Baseband Processor (tetra Etc.)
• Manufacturer: Consumer Microcircuits Limited

Advanced Digital Radio Baseband Processor
5.11.1 $00
5.11.2 $01
 2002 CML Microsystems Plc
Bits 7 and 6 control the frequency of the serial clock. Setting a serial clock frequency of MCLK/4
will cause the receive port to transmit at half the normal sample rate, i.e. 72kHz per channel
instead of 144kHz. Note: when these bits are changed, the serial clock frequency will not change
until the next sample clock.
Bit 5 will enable the bidirectional mode on port 1. This will cause read data requested by port 1 to
be returned on the CmdDat1 pin when port1 is configured as a fast serial bus.
Bits 4 and 3 select which signal is present on the SymClock pin.
Bits 2 to 0 will tristate the frame sync and data pins of each data port when selected.
Setting bit 7 high will bypass the 1/32 symbol delay on the receive data path.
Bit 6 will enable the clock stop hardware interlock mode, stopping the serial clock when the
transmit path is enabled and the FIFO is full.
Setting bit 5 high will enable the frame sync hardware interlock mode, generating frame sync
signals on the TXFS pin until the FIFO is full.
Bit 4 changes the polarity of the frame sync output pins.
Setting bit 3 high will cause read operations to the auxiliary RAM to increment the address pointer.
Setting this bit low causes write operations to increment the address pointer.
Bit 2 enables access to the auxiliary RAM.
Setting bit 1 high will cause read operations to the filter coefficient RAMs to increment the address
pointer. Setting this bit low causes write operations to increment the address pointer.
Bit 0 enables access to the filter coefficient RAMs.
Bit
Bit
Bit 7
0
0
1
1
Rx delay
Bypass
Serial Clock
7
Bit 6
7
0
1
0
1
Rate
ConfigCtrl1
ConfigCtrl2
6
clock stop
interlock
Enable
mode
Frequency
Reserved
MCLK/4
MCLK/2
6
MCLK
bidirectional
Enable
mode
frame sync
5
interlock
Enable
mode
5
Configuration Control Register 1
Configuration Control Register 2.
SymClock pin source
Active
frame
syncs
24
low
4
Bit 4
4
0
0
1
1
select
Increment
pointer on
Aux RAM
read
3
Bit 3
3
0
1
0
1
read port
Disable
Aux RAM
Enable
access
2
1
Codec Sample Clock (8kHz)
2
Sample Clock (144kHz)
Symbol Clock (18kHz)
read port
Disable
Increment
coefficient
Reserved
RAM on
1
2
Signal
read
1
Disable rx
coefficient
port
access.
Enable
0
RAM
0
CMX981
D/981/1