P60ARM-B/IG/GP1N Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1N Datasheet - Page 99

• Manufacturer Part Number: P60ARM-B/IG/GP1N
• Description: A Low Power, General Purpose 32 Bit RISC Microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

There is no parallel output from the bypass register.
A logic 0 is loaded from the parallel input of the bypass register in the CAPTURE-DR state.
8.6.2 ARM60 Device IdentiÞcation (ID) Code Register
Purpose: This register is used to read the 32-bit device identification code. No programmable
supplementary identification code is provided.
Length: 32 bits
The format of the ID register is as follows:
Please contact your supplier for the correct Device Identification Code.
Operating Mode: When the IDCODE instruction is current, the ID register is selected as the serial path
between TDI and TDO .
There is no parallel output from the ID register.
The 32-bit device identification code is loaded into the ID register from its parallel inputs during the
CAPTURE-DR state.
8.6.3 ARM60 Boundary Scan (BS) Register
Purpose: The BS register consists of a serially connected set of cells around the periphery of the device, at
the interface between the core logic and the system input/output pads. This register can be used to isolate
the core logic from the pins and then apply tests to the core logic, or conversely to isolate the pins from the
core logic and then drive or monitor the system pins.
Operating modes: The BS register is selected as the register to be connected between TDI and TDO only
during the SAMPLE/PRELOAD, EXTEST and INTEST instructions. Values in the BS register are used, but
are not changed, during the CLAMP and CLAMPZ instructions.
In the normal (system) mode of operation, straight-through connections between the core logic and pins are
maintained and normal system operation is unaffected.
In TEST mode (i.e. when either EXTEST or INTEST is the currently selected instruction), values can be
applied to the core logic or output pins independently of the actual values on the input pins and core logic
outputs respectively. On the ARM60 all of the boundary scan cells include an update register and thus all
of the pins can be controlled in the above manner. Additional boundary-scan cells are interposed in the scan
chain in order to control the enabling of tristateable buses.
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Boundary Scan Test Interface
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