SI91821 Vishay Siliconix, SI91821 Datasheet - Page 4

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SI91821

Manufacturer Part Number
SI91821
Description
Micropower 300-mA CMOS LDO Regulator With Error Flag
Manufacturer
Vishay Siliconix
Datasheet
Si91821
Vishay Siliconix
www.vishay.com
4
TIMING WAVEFORMS
PIN CONFIGURATION
PIN DESCRIPTION
Pin Number
1, 4
2
3
5
6
7
8
Name
ERROR
C
V
GND
SET
NOISE
V
SD
OUT
IN
Output voltage. Connect C
Input supply pin. Bypass this pin with a 2.2-mF ceramic or tantalum capacitor to ground.
Ground pin. Local ground for C
For fixed output voltage versions, this pin could be connected to GND. For adjustable output voltage version, this
voltage feedback pin sets the output voltage via an external resistor divider.
Noise bypass pin. For low noise applications, a 0.01-mF or larger ceramic capacitor should be connected from this pin
to ground.
By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to V
This open drain output is an error flag output which goes low when V
V
SD
ERROR
OUT
V
NOM =
V
v
GND
OUT
OUT
v
Figure 4.
IN
0.95 V
NOM
V
1
2
3
4
IH
OUT
Timing Diagram for Power-Up
between this pin and ground.
NOISE
MSOP-8
Top View
t
ON
t
DELAY
and C
OUT
.
8
7
6
5
Function
V
ERROR
SD
C
SET
IL
NOISE
t
DELAY
OUT
drops 5% below its nominal voltage.
IN
if unused.
S-51147–Rev. E, 20-Jun-05
Document Number: 71614

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