ACS104A Semtech Corporation, ACS104A Datasheet - Page 2

• Manufacturer Part Number: ACS104A
• Description: Acs104a Fiber Modem
• Manufacturer: Semtech Corporation

This device offers one high speed and three low speed full duplex
channels to the user in a completely transparent way, appearing as
4 full duplex channels.
Data from the TxD and low frequency channels is time
compressed in an internal FIFO and sent over the fiber link in a
burst within a predefined window. The two devices at each end of
the link automatically synchronise with each other such that the
transmit and receive windows are interleaved.
offers superior performance compared to continuous receive and
transmit systems, since the transmitted data does not cause noise
injection during the receiving time. The TxD input data of the
transmitting modem is also data compressed. The 3B4B encoding
method is used for communication between ACS104As, thus
ensuring that there is no DC component in the signal.
encoding and decoding is transparent to the user.
In the receiving modem, 3B4B encoding ensures easy extraction of
the bit-clock.
stored in the output memory.
expansion, de-jittering and frequency compensation functions. The
data is then decompressed and directed to the RxD output pin,
appearing after a minimal delay, in the same format as that
presented at the TxD pin at the far end.
The ACS104A is compatible with the ACS104 but offers over twice
the max data rate.
modes.
interfacing the device with external PIN / amplifier modules. The
setups refer to the pin settings for the TQFP44 package. The
PLCC28 pin settings will be the same with the unavailable pins
being internally pulled high.
Mode 1 - Dual Fiber LED/PIN mode
Setup : DP4=1, DP3=1, DP2=1, DP1=1
This is a twin-fiber mode where the LED is used for transmission
and a separate PIN Diode is used for reception. An example circuit
diagram showing the necessary connections is shown in figures 3
and 4.
Mode 2 - Preamp Voltage Input & LED Drive
Setup : DP4=0, DP3=1, DP2=0, DP1=0, NSB=0 (TQFP44 only)
This is a mode for use with external amplifier and PIN modules. An
LED is used for transmission and connected as normal with its
anode to LAP and cathode to LAN. The differential voltage from
an external PIN/TIA module is connected to PINN and PINP via
100pF capacitors to provide DC isolation. The signals should be
connected such that PINP is connected to the TIA output that goes
high when light is received. A single input can also be applied from
a single ended PIN/TIA by feeding the input to PINP only, PINN is
left floating. This mode uses the new NSB pin, in all other modes
this pin should be left disconnected or connected to VA+.
Mode 11 - Digital Data Input & LED Drive
Setup : DP4=1, DP3=0, DP2=1, DP1=0
This is a mode for use with external amplifier and PIN modules that
provide fully digital output levels. An LED is used for transmission
and connected as normal as shown in figure 4. The output from an
external PIN/TIA module is connected to CNT. The polarity of the
input should be such that CNT that goes high when light is
received.
The LED transmit current is not critical though it is important not to
exceed the LED manufacturer's recommendation for maximum
Operational Modes
LED current control
Transmitter and Receiver Functions
Advanced Communications
Additional modes are also described for new ways of
The received data is filtered, decoded, and then
The following sections detail the operating
Dual Fiber Modem for Asynchronous Data Rates from DC to 160kbps
The memory provides time
This technique
The
2
current. The current is controlled by a resistance Rtrc connected
between TRC and GND. The lower the value of Rtrc the greater
the current. The lower limit for Rtrc is 800
maximum is 40k .
The LED current is inversely proportional to Rtrc while Rtrc > 800 .
The ACS104A benefits from data compression circuitry which
reduces power consumption and improves the BER (Bit Error
Rate).
minimum TxD data-bit time of 10 sample-clocks. This defines the
maximum data rate:
Maximum data rate = sample-clock/10
However, an allowance must be made for any variation in the TxD
data-bit period to accommodate frequency variation and jitter.
Hence the maximum data rates specified in the following are
decreased by 10% to include a sufficient safety margin.
The ACS104A includes an input pulse shaper which ensures that
the system is very tolerant to jitter, and helps achieve a maximum
data-rate close to the theoretical maximum of sample-clock/10
(bps). The pulse shaper will expand data pulses of less than 10
clock-samples to meet the compression criteria. This is performed
on up to three consecutive data-bits which fail to meet the
minimum pulse width criteria.
Table 1. TxD Data-Rate Selection
Table 1. shows the maximum TxD data rate, which includes a 10%
tolerance margin, when using various frequency crystals, other
sample-clock frequencies may be generated by using the
appropriate value XTAL in combination with the divide constant
selected by DR(1:3) namely 15, 20, 40, 80 or 160. The advantage
of using a slower crystal and a lower sample clock is the reduced
power consumption of the device.
DR3 is internally held high in the PLCC28 package.
Three additional low frequency data channels are provided on the
ACS104A which are often used for the RS-232 handshake signals.
The RS-232 handshake signals comprise the set RTS, CTS, DTR
and DSR. These are treated as pass through data channels rather
than using local handshaking. Hence the status of inputs RTS and
DTR appear at the far-end outputs CTS and DSR respectively. An
extra data channel has also been provided in the TQFP44
package, which may be used for sending the RS232 Ring Indicator
signal, for example. The input and output lines are RII and RIO
respectively.
The transmission method employed on the ACS104A has been
designed to give low skew (1 - 2 data-bits) on the main RTS, CTS,
DTR and DSR hanshake signals relative to the main TxD/RxD data
channel, while maintaining low power consumption.
The handshake signals are updated by two stimuli:
i.
ii.
The maximum bandwidth for the handshake signals may be
Data-Rate Selection
RS-232 Handshake Signals / Low Frequency Data Channels
DR3
0
1
1
1
1
1
1
LED current = (100 / Rtrc) +/- 25 %
An internal interval timer at a frequency proportional to the XTAL; at
10.0MHz this is approximately 1.6ms.
Changes detected on RTS and DTR.
DR2
1
0
0
1
1
1
1
The compression technique employed, demands a
DR1
1
0
1
0
1
1
1
Clock
10MHz
10MHz
10MHz
10MHz
10MHz
20MHz
27MHz
XTAL
Sample
Clock
ACS104A Data Sheet
XTAL/80
XTAL/40
XTAL/20
XTAL/15
XTAL/15
XTAL/15
XTAL/160
Data Rate
Max TxD
while a practical
120kbps
162kbps
5.6kbps
11kbps
22kbps
45kbps
60kbps