ACS411CS Semtech Corporation, ACS411CS Datasheet - Page 20

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ACS411CS

Manufacturer Part Number
ACS411CS
Description
Acapella Optical Modem ic
Manufacturer
Semtech Corporation
Datasheet
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
In SERIAL mode, the device is configured to interface
with a serial microprocessor bus. The following
figures show the timing diagrams of write and read
accesses for this mode.
During read access the output data sdo (AD(0)) is
clocked out on the rising edge of SCLK (ALE) when
the active edge selection control bit CLKE (A(1)) is
uP Interface timing - SERIAL mode
Note: preliminary timing information. Timing values marked with * TBA.
A(0) = SDI
AD(0) = SDO
CSB
ALE = SCLK
R/W
Symbol
tpw1
tpw2
tsu1
tsu2
th1
th2
td1
td2
tp
Figure 10: Read access timing in SERIAL Mode.
A1
Setup SDI valid to SCLK
Setup CSB to SCLK
Hold SDI to SCLK
Hold SCLK
SCLK low time
SCLK high time
CLKE = 1) to SDO valid
(CSB
Delay SCLK
Delay CSB
Time between consecutive accesses
Z
A2
to CSB )
A3
Parameter
to SDO High-Z
to CSB
(SCLK
A4
A5
for
20
A6
0, and on the falling edge when CLKE is 1. Address,
read/write control bit and write data are always
clocked into the interface on the rising edge of SCLK.
Both input data sdi and clock SCLK are oversampled
, filtered and synchronized to the system clock CLKX.
The serial interface clock (SCLK) is not required to
run when no access is performed (CSB = 1).
Min
10 *
10 *
10 *
10 *
240
240
250
D0
D1
Typ
D2
Max
20 *
120
D3
D4
D5
D6
Z

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