ACS8509 Semtech Corporation, ACS8509 Datasheet - Page 41

• Manufacturer Part Number: ACS8509
• Description: Synchronous Equipment Timing Source for Sonet or SDH Network Elements
• Manufacturer: Semtech Corporation

Pre-Locked(2) mode
This state is very similar to the Pre-Locked state. It is
entered from the Holdover state when a reference source
has been selected and applied to the phase locked loop.
It is also entered if the device is operating in Revertive
mode and a higher-priority reference source is restored.
Upon applying a reference source to the phase locked
loop, the ACS8509 will enter the Locked state in a
maximum of 100 seconds, as defined by GR-1244-CORE
specification, if the selected reference source is of good
quality.
If the device cannot achieve lock within 100 seconds, it
reverts to Holdover mode and another reference source is
selected.
Protection Facility
The ACS8509 supports redundancy protection. The
primary functions of this include:
- Alignment of the priority tables of both Master and Slave
ACS8509 devices so as to align the selection of reference
sources of both Master and Slave ACS8509 devices.
- Alignment of the phases of the 8 kHz and 2 kHz clocks in
both Master and Slave ACS8509 devices to within one
cycle of the 77.76 MHz internal clock.
When two ACS8509 devices are to be used in a
redundancy-protection scheme within an NE, one will be
designated as the Master and the other as the Slave. It is
expected that an NE will use the T
internal operations because the T
to feed an SSU/BITS system. An SSU/BITS will not be
bothered by phase differences between signals arriving
from different sources because it typically incorporates
line build-out functions to absorb phase differences on
reference inputs. This means that the phasing of the
composite clocks between two ACS8509 devices do not
have to be mutually-aligned.
The same is not true, however, of the T
(O1 ,O2, O3, Frame clock and Multi-Frame clock). It is
usually important to align the phases of all equivalent
T
switch-over from one device to another does not affect the
internal operations of the NE. Both ACS8509 devices will
produce the same signals, which will be routed around the
NE to the various consumers (clock sinks). With the
possible exception of a through-timing mode, the signals
from the Master device will be used by all consumers,
Revision 2.00/January 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
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signals generated by different sources so that
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output is intended
output for its
output signals
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unless the Master device fails, when each consumer will
switch over to the signals generated by the Slave device.
Switchover to a new T
possible. This requires the signals of both
to be phase aligned at each consumer. Phase alignment
requires frequency alignment. To ensure that both
devices can generate output clocks locked to the same
source, both devices are supplied with the same
reference sources on the same input ports and will have
identical priority tables.
Failures of selected reference sources will result in both
ACS8509 devices making the same updates to their
priority tables as availability information will be updated in
both devices. Although, in principle, the priority tables will
be the same if the same reference sources are used on
the same input port on each device, in practice, this is
only true if the reference sources actually arrive at each
device - failures of a source seen only by one device and
not by the other, such as could be caused, for example, by
a backplane connector failure, would result in the priority
tables becoming misaligned. It is thus necessary to force
the priority tables to be aligned under normal operating
conditions so that the devices can make the same
decisions - this can be achieved by loading the availability
seen by one device (via the sts_reference_sources
register) into the cnfg_sts_remote_sources_valid register
of the other device.
Another factor which could affect hit-less switching is the
frequency of the local oscillator clock used by each
ACS8509 device: these clocks are not mutually aligned
and, whilst this has no impact on the frequency of the
output clocks during locked mode, it could cause the
output frequencies to diverge during Holdover mode if no
action were taken to avoid it.
In order to maintain alignment of the output frequencies
of each
device's 6.48 MHz output is fed into the Slave device on
its SEC3 pin, whilst the Multi-Frame Sync (2 kHz) output is
fed to the Sync2k input of the Slave. In this way, the Slave
locks to the master's output and remains locked whilst
the Master moves between operating states. Only when
the Master fails does the Slave use its own reference
inputs - should the Master have been in the Holdover
state, the Slave device will see the same lack of reference
sources and also enter the Holdover state. This scheme
also provides a convenient way to phase-align all T
output clocks in Master and Slave devices, and also to
detect the failure of the Master device.
ACS8509
device even during Holdover, the Master
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clock should be as hitless as
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