USB2230 SMSC Corporation, USB2230 Datasheet - Page 17

• Manufacturer Part Number: USB2230
• Description: (USB2229 / USB2230) 5th Generation Hi-Speed USB Flash Media and IrDA Controller
• Manufacturer: SMSC Corporation

5th Generation Hi-Speed USB Flash Media and IrDA Controller with Integrated Card Power FETs
Datasheet
SMSC USB2229/USB2230
Memory Data Bus
Memory Address
Memory Address
Memory Address
Crystal Output
NAME
Bus
Bus
Bus
SEL_CLKDRV
SYMBOL
MA[15:3]
TX_POL
MD[7:0]
XTAL2
MA3/
MA2/
Table 6.1 USB2229/USB2230 Pin Descriptions
MEMORY/IO INTERFACE
BUFFER
I/O8PU
I/O8PD
OCLKx
TYPE
IO8
O8
DATASHEET
17
24Mhz Crystal
This is the other terminal of the crystal, or left open
when an external clock source is used to drive
XTAL1/CLKIN. It may not be used to drive any external
circuitry other than the crystal circuit.
When ROMEN bit of GPIO_IN1 register = 0, these
signals are used to transfer data between the internal
CPU and the external program memory.
These pins have internally controlled weak pull-up
resistors.
These signals address memory locations within the
external memory.
MA3 Addresses memory locations within the external
memory.
During nRESET assertion, TX_POL will select the
operating polarity of the IR LED (active high or active
low) and the weak pull-up resistor will be enabled.
When nRESET is negated, the value on this pin will be
internally latched and this pin will revert to MA3
functionality, the internal pull-up will be disabled.
MA2 Addresses memory locations within the external
memory.
SEL_CLKDRV. During nRESET assertion, this pins will
select the operating clock mode (crystal or externally
driven clock source), and a weak pull-down resistor is
enabled. When nRESET is negated, the value will be
internally latched and this pin will revert to MA2
functionality, the internal pull-down will be disabled.
‘0’ = Crystal operation (24MHz only)
‘1’ = Externally driven clock source (24MHz or 48MHz)
Note:
1. IDLE bit (PCON.0) is 1.
2. INT2 is negated
3. SLEEP bit of CLOCK_SEL is 1.
If the latched value is ‘0’, then the MA2 pin will function
identically to the MA[15:3] pins at all times (other than
during nRESET assertion).
If the latched value is ‘1’, then the MA2 pin is
tri-stated when the following conditions are
true:
DESCRIPTION
Revision 1.3 (02-13-06)