USBLC6-2 STMicroelectronics, USBLC6-2 Datasheet - Page 9
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USBLC6-2
Manufacturer Part Number
USBLC6-2
Description
VERY LOW CAPACITANCE ESD PROTECTION
Manufacturer
STMicroelectronics
Datasheet
1.USBLC6-2.pdf
(14 pages)
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USBLC6-2
2.6
Figure 16. PSpice model
Note:
Figure 17. PSpice parameters
CJ0
IBV
D+in
GND
D-in
BV
RS
VJ
TT
M
0.3333
Dlow
0.9p
0.1u
1m
0.2
0.6
50
PSpice model
Figure 16.
defined by the PSpice parameters given in
This simulation model is available only for an ambient temperature of 27 °C.
LGND
LI/O
LI/O
0.3333
Dhigh
2.0p
0.52
0.1u
1m
0.6
50
shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are
RGND
Dzener
0.3333
RI/O
RI/O
0.84
0.1u
40p
7.3
1m
0.6
RGND
LGND
MODEL = Dlow
RI/O
LI/O
MODEL = Dlow
110m
750p
550p
60m
MODEL = Dzener
Figure 18. USBLC6-2 PCB layout
GND
D+in
D-in
MODEL = Dhigh
MODEL = Dhigh
Figure 17.
1
considerations
USBLC6-2
RI/O
RI/O
RI/O
Technical information
LI/O
LI/O
D+out
V
D-out
LI/O
BUS
C
BUS
= 100nF
D+out
VBUS
D-out
9/14