USBN9604 National Semiconductor, USBN9604 Datasheet - Page 15

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USBN9604

Manufacturer Part Number
USBN9604
Description
USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support
Manufacturer
National Semiconductor
Datasheet

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3.0 Parallel Interface
3.2 MULTIPLEXED MODE
Multiplexed mode uses the control pins CS, RD, WR, the address latch enable signal ALE and the bidirectional address data
bus AD7-0 as shown in Figure 6. This mode is selected by tying MODE1 to GND and MODE0 to V
into the ADDR register when ALE is high. Data is output/input with the next active RD or WR signal. All registers are directly
accessible in this interface mode.
Figure 7 shows basic timing of the interface in Multiplexed mode.
AD7-0
ALE
CS
WR
RD
RD or WR
AD7-0
ALE
CS
(Continued)
Figure 7. Multiplexed Mode Basic Read/Write Timing
Figure 6. Multiplexed Mode Block Diagram
EN
ADDR
ADDR
15
Data Out
Address
DATA
Data In
0x3F
0x00
CC
Register File
. The address is latched
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