ADP3155 Analog Devices, ADP3155 Datasheet - Page 10

• Manufacturer Part Number: ADP3155
• Description: 5-Bit Programmable Triple Power Supply Controller for Pentium III Processors
• Manufacturer: Analog Devices

ADP3155
high side FET, however, is turned on with only 12 V – 5 V = 7 V.
Checking the typical output characteristics of the device in the
data sheet shows that for an output current of 10 A, and at a
V
above the one specified at a V
crease due to the reduced gate drive can be neglected. The
specified R
ture of +140 C must be modified by an R
using the graph in the data sheet. In this case:
Using this multiplier, the expected R
14 m = 24 m .
The high side FET dissipation is:
where the second term represents the turn-off loss of the FET.
(In the second term, Q
the gate for turn-off and I
sheet, Q
provided by the ADP3155 is about 1 A.)
The low side FET dissipation is:
(Note that there are no switching losses in the low side FET.)
To maintain an acceptable MOSFET junction temperature,
proper heat sinks should be used. The Thermalloy 6030 heat
sink has a thermal impedance of 13 C/W with convection cool-
ing. With this heat sink, the junction-to-ambient thermal imped-
ance of the chosen high side FET
sink-to-ambient) + 2 C/W (junction-to-case) + 0.5 C/W (case-
to-heat sink) = 15.5 C/W.
At full load, and at +50 C ambient temperature, the junction
temperature of the high side FET is:
The same heat sink may be used for the low side FET, e.g., the
Thermalloy type 7141 ( = 20.3 C/W). With this heat sink, the
junction temperature of the low side FET is:
All of the above-calculated junction temperatures are safely
below the +175 C maximum specified junction temperature of
the selected FETs.
The maximum operating junction temperature of the ADP3155
is calculated as follows:
where
ADP3155 and P
is equal to 110 C/W and I
follows:
The result is:
C
In continuous inductor-current mode, the source current of the
high side MOSFET is a square wave with a duty ratio of V
V
GS
lN
P
IN
DFETHS
. To keep the input ripple voltage at a low value, one or more
Selection and Input Current di/dt Reduction
of 7 V, the V
JA
G
= I
is about 50 nC–70 nC and the gate drive current
is the junction-to-ambient thermal impedance of the
DS(ON)
T
P
T
RMSHS
JHSMAX
DR
JLSMAX
P
T
= (C
DS
DFETLS
DR
JICMAX
at the expected highest FET junction tempera-
2
is 0.15 V. This gives an R
is the drive power. From the data sheet,
R
= T
= T
RSS
DS(ON)
G
= I
= T
T
R
A
A
+ C
is the gate charge to be removed from
JICMAX
G
DS(ON)MULT
+
IC
+
RMSLS
A
is the gate current. From the data
+ 0.5 V
ISS
= 2.7 mA. P
+
JAHS
GS
JALS
)V
2
= +86 C
JA
of 10 V, so the resistance in-
R
CC
P
P
DS(ON)
(I
IN
DFETLS
2
DFETHS
JAHS
IC
DS(ON)
f
= 1.7
I
MAX
LPEAK
V
CC
will be 13 C/W (heat
DR
= 1.7 W
= 307 mW
= +106 C
DS(ON)
= +105 C
+ P
at +140 C is 1.7
Q
can be calculated as
DS(ON)
G
f
DR
MIN
)
multiplier,
/I
only slightly
G
~ 3.72 W
OUT
JA
/
–10–
capacitors with low equivalent series resistance (ESR) and ad-
equate ripple-current rating must be connected across the input
terminals. The maximum rms current of the input bypass
capacitors is:
For an FA-type capacitor with 2700 F capacitance and
10 V voltage rating, the ESR is 34 m and the allowed ripple
current at 100 kHz is 1.94 A. At +105 C, at least four such
capacitors must be connected in parallel to handle the calculated
ripple current. At +50 C ambient, however, a higher ripple
current can be tolerated, so three capacitors in parallel are
adequate.
The ripple voltage across the three paralleled capacitors is:
To further reduce the effect of the ripple voltage on the system
supply voltage bus and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/ s, an additional
small inductor (L > 1.7 H @ 10 A) should be inserted between
the converter and the supply bus (see Figure 2).
Feedback Loop Compensation Design for Active Voltage
Positioning
Optimized compensation of the ADP3155 allows the best pos-
sible containment of the peak-to-peak output voltage deviation.
Any practical switching power converter is inherently limited by
the inductor in its output current slew rate to a value much less
than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and this will produce an output voltage deviation equal to the
ESR of the output capacitor array times the load current change.
To correctly implement active voltage positioning, the low fre-
quency output impedance (i.e., the output resistance) of the
converter should be made equal to the maximum ESR of the
output capacitor array. This can be achieved by having a single
pole roll-off of the voltage gain of the g
the pole frequency coincides with the ESR zero of the output
capacitor. A gain with single pole roll-off requires that the g
amplifier output pin be terminated by the parallel combination
of a resistor and capacitor. The required resistor value can be
calculated from the equation:
where:
and where the quantities 16.4 k and 275 k are characteristic
of the ADP3155 and the value of the current sense resistor, R
has already been determined as above.
Although a single termination resistor equal to R
the proper voltage positioning gain, the dc biasing of that resis-
tor would determine how the regulation band is centered (i.e.,
offset). Note that sometimes the specified regulation band is
asymmetrical with respect to the nominal VID voltage. With the
ADP3155, the offset is already considered part of the design
procedure—no special provision is required. To accomplish the
V
140 mV p-p
CINRPL
= I
OMAX
Rt
I
CINRMS
TOTAL
[ESR
R
C
IN
= 0.5 I
275
275
16 4 .
/3 +D
k
k
k
OMAX
MAXHF
V
HI
–
R
Rt
Rt
–
= 7 A rms
CS
/(3 C
V
m
TOTAL
TOTAL
LO
error amplifier, where
I
IN
OMAX
f
MIN
C
)] =
would yield
REV. A
m
CS
,