ADP3163 Analog Devices, ADP3163 Datasheet - Page 11

• Manufacturer Part Number: ADP3163
• Description: 5-Bit Programmable 2-/3-Phase Synchronous Buck Controller
• Manufacturer: Analog Devices

The critical capacitance limit for this circuit is 6.93 mF, while
the actual capacitance of the nine Rubycon capacitors is 9
2200 F = 19.8 mF. In this case, the capacitance is safely above
the critical value.
Multilayer ceramic capacitors are also required for high-frequency
decoupling of the processor. The exact number of these MLC
capacitors is a function of the board layout space and parasitics.
Typical designs use twenty to thirty 10 F MLC capacitors
located as close to the processor power pins as is practical.
Feedback Loop Compensation Design for ADOPT
Optimized compensation of the ADP3163 allows the best pos-
sible containment of the peak-to-peak output voltage deviation.
Any practical switching power converter is inherently limited by
the inductor in its output current slew rate to a value much less
than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and assuming that the capacitance of the output capacitor is
larger than the critical value defined by Equation 13, this will
produce a peak output voltage deviation equal to the ESR of the
output capacitor times the load current change.
The optimal implementation of voltage positioning, ADOPT,
will create an output impedance of the power converter that is
entirely resistive over the widest possible frequency range, includ-
ing dc, and equal to the maximum acceptable ESR of the output
capacitor array. With the resistive output impedance, the output
voltage will droop in proportion with the load current at any
load current slew rate; this ensures the optimal positioning and
allows the minimization of the output capacitor bank.
With an ideal current-mode-controlled converter, where the
average inductor current would respond without delay to the
command signal, the resistive output impedance could be
achieved by having a single-pole roll-off of the voltage gain of
the voltage-error amplifier. The pole frequency must coincide
with the ESR zero of the output capacitor bank. The ADP3163
uses constant frequency current-mode control, which is known
to have a nonideal, frequency dependent command signal to
inductor current transfer function. The frequency dependence
manifests in the form of a pair of complex conjugate poles at
one-half of the switching frequency. A purely resistive output
impedance could be achieved by canceling the complex conjugate
poles with zeros at the same complex frequencies and adding a
third pole equal to the ESR zero of the output capacitor. Such a
compensating network would be quite complicated. Fortunately, in
practice it is sufficient to cancel the pair of complex conjugate
poles with a single real zero placed at one-half of the switching
frequency. Although the end result is not a perfectly resistive
output impedance, the remaining frequency dependence causes
only a small percentage of deviation from the ideal resistive
response. The single-pole and single-zero compensation can be
easily implemented by terminating the g
the parallel combination of a resistor (R
work. The value of the terminating resistor R
previously; the capacitance and resistance of the series RC net-
work are calculated as follows:
C
19 8
OC
.
mF
6 31
.
C
OUT
k
1 5
R
.
T
m
R
OUT
600
f
OSC
n
kHz
3
R
T
6 31
.
T
m
) and a series RC net-
error amplifier with
k
T
was determined
4 4
.
nF
(14)
The nearest standard value of C
zero-setting resistor in series with the compensating capacitor is:
The nearest standard 5% resistor value is 330 . Note that this
resistor is only required when C
25% or less). In this example, C
therefore be omitted.
Power MOSFETs
In this example, six N-channel power MOSFETs must be used;
three as the main (control) switches, and the remaining three as
the synchronous rectifier switches. The main selection parameters
for the power MOSFETs are V
minimum gate drive voltage (the supply voltage to the ADP3414)
dictates whether standard threshold or logic-level threshold
MOSFETs must be used. Since V
old MOSFETs (V
The maximum output current I
ment for the power MOSFETs. When the ADP3163 is operating
in continuous mode, the simplifying assumption can be made
that in each phase one of the two MOSFETs is always conduct-
ing the average inductor current. For V
1.45 V, the duty ratio of the high-side MOSFET is:
The duty ratio of the low-side (synchronous rectifier) MOSFET is:
The maximum rms current of the high-side MOSFET during
normal operation is:
The maximum rms current of the low-side MOSFET during
normal operation is:
The R
dissipation. If 10% of the maximum output power is allowed for
MOSFET dissipation, the total dissipation in the eight MOSFETs
of the four-phase converter will be:
D
HSF
7 7
0 1 1 394
R
D
I
I
P
65
HSF MAX
LSF MAX
.
DS(ON)
.
FET TOTAL
Z
LSF
3
A
A
(
(
(
V
.
V
OUT
1
for each MOSFET can be derived from the allowable
IN
)
0 125
)
f
0 875
0 125
OSC
.
)
D
.
.
V
n
I
HSF
GS(TH)
I
n
HFS M AX
0 1
1 5
O
12
.
.
65
C
(
V
V
OC
1
20 4
87 5 . %
V
A
< 2.5 V) are strongly recommended.
D
MIN
.
HSF
3 65
)
12 5
10 9
9 06
A
.
. %
O
.
OC
GS(TH)
OUT
600
OUT
determines the R
I
D
D
O
A
W
is 4.7 nF. The resistance of the
1
GATE
A
LSF
HSF
2
2
approaches C
kHz
>> C
, Q
I
3
L RIPPLE
IN
3
<8 V, logic-level thresh-
(
G
7 7
= 12 V and V
CRIT
and R
.
I
4 7
O
.
2
A
ADP3163
, and R
)
2
nF
DS(ON)
DS(ON)
CRIT
338
Z
. The
(within
require-
can
OUT
=
(20)
(15)
(16)
(17)
(18)
(19)