ADP3204 Analog Devices, ADP3204 Datasheet - Page 4

• Manufacturer Part Number: ADP3204
• Description: 3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs
• Manufacturer: Analog Devices

ADP3204
Parameter
SHIFT SETTING
SHIFT CONTROL INPUTS
LOW SIDE DRIVE CONTROL
OVER/REVERSE VOLTAGE
NOTES
1
2
3
4
5
6
7
8
9
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
Two test conditions: 1) PWRGD is OK but forced to fail by applying an out-of-the-Core Good-window voltage (V
Measured from 50% of VID code transition amplitude to the point where V
40 mVpp amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.
Measured between the 30% and 70% points of the output voltage swing.
COREFB pin right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking delay
time. 2) PWRGD is forced to fail (V
that BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified blanking delay time.
Guaranteed by design
Measured between DACRAMP and DACOUT pins.
DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design.
COREFB pin has a resistor divider to GND whose resistance is 41.3 k
Battery-Shift Current
Battery-Shift Reference Voltage
Deep Sleep-Shift Current
Deep Sleep-Shift Reference
Deeper Sleep-Shift Current
Deeper Sleep-Shift Reference
BOM Threshold
DPSLP Threshold
DPRSLP Mode Threshold
Output Voltage (CMOS Output)
Output Current
PROTECTION CORE FEEDBACK
Overvoltage Threshold
Reverse-Voltage Threshold
Output Current
Voltage
(CMOS Input)
(CMOS Input)
(CMOS Input)
(Open-Drain Output)
Voltage
8
COREFB, BAD
= 1.0 V at V
Symbol
I
V
I
V
I
I
V
V
V
V
V
I
V
V
I
RAMPB
RAMPD
REGDPR
COREFBDPR
DRVLSD
CLAMP
BSHIFT
DSHIFT
DPRSHIFT
BOM
DSLP
DPRSLP
DRVLSD
COREFB, OVP
COREFB, RVP
VID
, I
, I
= 1.25 V setting) but gets into the Core Good-window (V
CS+B
CS+D
8
9
9
Conditions
V
I
DPSLP = H
V
I
DPSLP = L
I
V
I
DPRSLP = H
DPRSLP = H
DPRSLP = L
DPRSLP = H, V
DPRSLP = L, V
V
V
V
V
BSHIFT
DSHIFT
DPRSHIFT
DPRSHIFT
(typ), guaranteed by design.
VID
VID
VID
COREFB
COREFB
COREFB
COREFB
DACOUT
= 1.25 V
= 1.25 V
= 1.25 V,
–4–
= –100 µA, BOM = L
= –100 µA, BOM = H
= 2.2 V, V
= V
settles within ± 1% of its steady state value.
= –100 µA, DPRSLP = H
= –100 µA,
DAC
, V
DRVLSD
DRVLSD
CLAMP
CLAMP
= 1.5 V
= 1.5 V
= 1.5 V
= 1.5 V
COREFB, BAD
Min
–92.5
–92.5
–90
110
0
0.7 V
+0.4
–0.4
2
COREFB, GOOD
= 1.0 V at V
CC
Typ
= 1.25 V) right after the moment
–100
V
–100
V
–100
130
V
V
V
V
2.0
–0.3
6
DAC
DAC
DAC
CC
CC
CC
VID
/2
/2
/2
= 1.25 V setting) to the
Max
–107.5
–107.5
–110
150
0.4
V
10
CC
Unit
mA
V
mA
V
µA
µA
V
V
V
V
V
V
mA
mA
V
V
µA
mA
REV. 0