ADP3421JRU Analog Devices, ADP3421JRU Datasheet - Page 4

• Manufacturer Part Number: ADP3421JRU
• Description: Geyserville-Enabled DC-DC Converter Controller for Mobile CPUs
• Manufacturer: Analog Devices

ADP3421
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +7 V
UVLO Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
All Other Inputs/Outputs . . . . . . . . . . . . . . . . . . VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . 0°C to 100°C
Junction Temperature Range . . . . . . . . . . . . . . . 0°C to 150°C
θ
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . 300°C
Model
ADP3421JRU 0°C to 100°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3421 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W
Mnemonic
VHYS
CLSET
LTO
LTI
LTB
VID4
VID3
VID2
VID1
VID0
CLKDRV
CLKFB
IODRV
IOFB
Temperature
Range
ORDERING GUIDE
Function
Core Comparator Hysteresis Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to
ground programs at a 1:1 ratio the current that is alternately switched into and out of the RAMP pin.
Current Limit Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to ground programs
a current that is gained up by 3:1 flowing out of the CS– pin, assuming the current limit comparator is not
triggered.
Level Translator Output. This pin must be tied through a pull-up resistor to the voltage level desired for the
output high level. That voltage cannot be less than 1.5 V.
Level Translator Input. This pin should be driven from an open drain/collector signal. The pull-up current is
provided by the pull-up resistor on the LTO pin. However, the pull-up current will be terminated when the
LTI pin reaches 1.5 V.
Level Translator Bypass. For operation of the level translator with high-speed signals, this pin should be by-
passed to ground with a large value capacitor.
VID Input. Most significant bit.
VID Input
VID Input
VID Input
VID Input. Least significant bit.
2.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to
keep the CLKFB node regulated at 2.5 V.
2.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose
base is driven by the CLKDRV pin.
1.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to
keep the IOFB node regulated at 1.5 V.
1.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose
base is driven by the IODRV pin.
Package
Description
Thin Shrink Small RU-28
Outline (TSSOP)
PIN FUNCTION DESCRIPTIONS
Package
Option
CLKDRV
CLKFB
CLSET
IODRV
VHYS
PIN CONFIGURATION
IOFB
VID4
VID3
VID2
VID1
VID0
LTO
LTB
LTI
10
11
12
13
14
1
2
3
4
5
6
7
8
9
(Not to Scale)
ADP3421
TOP VIEW
WARNING!
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CS+
REG
VCC
OUT
GND
DACOUT
CORE
SSC
SSL
UVLO
PWRGD
SD
CS–
RAMP
ESD SENSITIVE DEVICE