HV9606 Supertex, Inc., HV9606 Datasheet - Page 7

• Manufacturer Part Number: HV9606
• Description: Switchmode PWM Controller
• Manufacturer: Supertex, Inc.

Functional Description,
Error Amplifier
The error amplifier has a minimum gain bandwidth of 1MHz. The
inverting and non-inverting inputs are available respectively at
FB and NI pins and the amplifier output is available at the COMP
pin. Maximum application flexibility is provided by having all
terminals of the error amplifier available. The design of the error
amplifier prevents its output from saturating to the high rail (V
thus providing very fast slew recovery capability.
Soft Start Control Circuit
The soft start circuit provides a nominal constant current output
of 10µA at the SS pin for charging a capacitor connected to this
pin. The instantaneous voltage on the SS pin determines the
high limit of the error amplifier, thus forcing the PWM to start at
minimum output duty cycle and slowly increase the duty cycle
until a stable closed loop operation is achieved. The value of the
capacitor should be selected to achieve this stable closed loop
operation before the voltage on the SS pin exceeds 1.2V at
maximum output load on the DC/DC converter.
Soft start can only be initiated if the STATUS output of the
SUPERVISOR circuit is low. The SS pin is pulled low, discharg-
ing the capacitor and engaging soft restart whenever the peak
current sense limit is exceeded or the VX2 UVLO detects a low
gate drive voltage.
PWM Circuit
The current mode PWM circuit operates at one half the oscillator
frequency with a duty cycle guaranteed not to exceed 50%. Its
minimum pulse width (typically 130nSec) provides a wide dy-
namic control range especially when operating at low frequen-
cies.
For the dynamic control range required by a given application the
maximum operating frequency can be determined using the
following equations.
t
f
Where t
V
and P
is the worst case minimum gate drive output duty cycle (195nSec),
f
the maximum oscillator frequency.
Supervisor Circuit
Designers may use this voltage monitor circuit for various
applications. The supervisor circuit controls the function of the
soft start circuit, which will be enabled when the STATUS output
pin is in a low state. The STATUS output pin is low when the
voltage on the SENSE pin is less than 0.85V
ON
OSC
PWM
IN(MIN)
= ( V
= 2 f
is the maximum gate drive switching frequency and f
OUT(MIN)
are the maximum and minimum input voltage, P
ON
IN(MAX)
PWM
is the maximum gate drive output on time, V
< 1 / t
are the maximum and minimum output power, D
/ V
IN(MIN)
ON
) x ( P
OUT(MAX)
/ P
OUT(MIN)
) x D
continued:
REF
– 100mV.
MIN
IN(MAX)
OUT(MAX)
OSC
and
DD
MIN
is
)
7
The supervisory circuit can be used to monitor the output voltage
of the DC/DC converter. When used in this manner the STATUS
output pin may be used as a WATCHDOG to reset a micro
controller when ever its supply voltage decays to a programmed
voltage level below which unpredictable operation may result.
Using it in this manner in a non-isolated topology, where the
output voltage is used for bootstrapping V
start as long as the output is within programmed limits, thereby
providing a rapid restart after a short duration input voltage
dropout. This allows the minimization of both input and output
capacitors for a given system hold up time requirement. In an
Isolated topology, sizing the V
greater than the output hold up time requirement will similarly
permit the minimization of the input and output capacitors.
The supervisory circuit can also be used as a high accuracy low
input voltage detection and inhibit circuit by connecting the
STATUS pin to the SS pin. Since the status pin has a 10mA
internal pull up it will double the charging current of the soft start
capacitor, thus the soft start capacitor value needs to be doubled
for the same soft start time. The SENSE pin may be connected
through a resistor divider to any monitored voltage source (other
than the output of the HV9606 based DC/DC converter) or to a
logic output. When the voltage on the SENSE pin falls below the
nominal threshold of 0.85V
low, thereby inhibiting the gate drive output and shutting down
the converter. The oscillator will operate even though the GATE
output is held low and the SYNC I/O pin will maintain synchroni-
zation with other system components or provide a clock signal to
the system.
Shut Down / Inhibit Operation
The HV9606 may be shut down or inhibited depending on the
system requirements.
Pulling the STOP pin down to SGND will shut down the HV9606,
placing it in a zero power (leakage only) mode where even the
oscillator is halted. This pull down may be accomplished with a
discrete MOSFET, an optocoupler, or the open drain/collector
output of a logic gate with at least 20V breakdown rating. Using
this shut down method will cause the SYNC pin to be pulled low,
thus synchronization of other components connected to the
SYNC line will be lost.
Provided the input voltage remains above the programmed stop
threshold, inhibit of the PWM can be achieved by pulling the SS
pin low to SGND, thereby forcing the gate drive output to a
permanent low state and guaranteeing a soft restart when SS pin
pull down is released. The internal start up regulator will power
the HV9606 thus the oscillator will operate and the SYNC I/O pin
will maintain synchronization with other system components or
provide a clock signal to the system. This pull down could be
accomplished with a discrete MOSFET, an optocoupler, or the
open drain/collector output of a logic gate with at least a 5V
breakdown rating.
REF
– 75mV, the SS pin will be pulled
DD
capacitor for a hold up time
DD
, it will inhibit soft
HV9606