AAT2784 Analogic Corporation, AAT2784 Datasheet - Page 15

• Manufacturer Part Number: AAT2784
• Manufacturer: Analogic Corporation

Evaluation Board Schematic
PGND
SystemPower
verter switching losses. For the condition where the
step-down converter is in dropout at 100% duty cycle,
the total device dissipation reduces to:
Since R
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range. Given the
total losses, the maximum junction temperature can be
derived from the θ
is 50°C/W.
Layout
The suggested PCB layout for the AAT2784 is shown in
Figures 2 and 3. The following guidelines should be used
to help ensure a proper layout.
1. The power input capacitors (C5 and C8) should be
2784.2007.11.1.1
V
EN1
EN2
EN3
IN
connected as closely as possible to VP1_2, VP3 and
PGND1,2,3 as shown in Figure 2.
placement of VP1_2 and VP3 for all converters,
proper decoupling is not possible with just one input
capacitor.
1
1
2
3
1
2
3
1
2
3
1
DS(ON)
, quiescent current, and switching losses all
10μF
P
C5
TOTAL
T
J(MAX)
TM
JA
10μF
= I
C4
for the TDFN34-16 package, which
= P
O
10μF
2
C1
TOTAL
· R
R7
0
DSON(H)
· Θ
Figure 1: AAT2784 Evaluation Board Schematic.
JA
+ I
+ T
Q
1
2
3
4
5
6
7
8
AMB
· V
U1
PGND2
FB2
EN1
EN2
GND
VIN
EN3
FB3
Due to the pin
IN
PGND3
AAT2784
PGND1
VP1_2
w w w . a n a l o g i c t e c h . c o m
LX2
VP3
LX1
FB1
LX3
16
15
14
13
12
11
10
9
LX3
C8
10μF
1
2. C1 and R7 are optional low pass filter components
3. C2 and L1, C6 and L2, C10 and L3 should be con-
4. The feedback trace or FB pin should be separate
5. The resistance of the trace from the load returns to
6. Connect unused signal pins to ground to avoid
7. For good thermal coupling, PCB vias are required
1.5μH
3-Channel Step-Down DC/DC Converter
L3
56pF
C9
LX2
for the IN supply pin for the device if additional noise
decupling is required in a noisy system
nected as closely as possible. The connection of
L1, 2, 3 to the LX1, 2, 3 pin should be as short as
possible.
from any power trace and connect as closely as pos-
sible to the load point. Sensing along a high-current
load trace will degrade DC load regulation.
PGND1, 2 and 3 should be kept to a minimum. This
will help to minimize any error in DC regulation due
to differences in the potential of the internal signal
ground and the power ground.
unwanted noise coupling.
from the pad for the TDFN paddle to the bottom
ground plane. The via diameter should be 0.3mm to
0.33mm and positioned on a 1.2mm grid.
1
59K
59K
R5
R6
LX1
1
1
C10
10μF
V
4.7μH
OUT3
L1
100pF
PRODUCT DATASHEET
C3
4.7μH
L2
29.4K
133K
R1
R2
100pF
AAT2784
C7
1
C2
4.7μF
V
OUT1
29.4k
133k
R4
R3
C6
4.7μF
1
1
V
PGND
OUT2
15