OPA689 Burr-Brown, OPA689 Datasheet - Page 14

• Manufacturer Part Number: OPA689
• Description: Wideband / High Gain VOLTAGE LIMITING AMPLIFIER
• Manufacturer: Burr-Brown

ESD PROTECTION
ESD damage is known to damage MOSFET devices, but any
semiconductor device is vulnerable to ESD damage. This is
particularly true for very high speed, fine geometry processes.
ESD damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device. In
precision operational amplifiers, this may cause a noticeable
degradation of offset voltage and drift. Therefore, ESD
handling precautions are required when handling the OPA689.
OUTPUT LIMITERS
The output voltage is linearly dependent on the input(s)
when it is between the limiter voltages V
(pin 5). When the output tries to exceed V
corresponding limiter buffer takes control of the output
voltage and holds it at V
Because the limiters act on the output, their accuracy does
not change with gain. The transition from the linear region
of operation to output limiting is sharp—the desired output
signal can safely come to within 30mV of V
Distortion performance is also good over the same range.
The limiter voltages can be set to within 0.7V of the supplies
(V
least 200mV apart (V
When pins 5 and 8 are left open, V
Voltage Limit; the minimum values are in the spec table.
Looking at Figure 7 for the zero bias current case will show
the expected range of (V
room).
When the limiter voltages are more than 2.1V from the
supplies (V
use simple resistor dividers to set V
Make sure you include the Limiter Input Bias Currents
(Figure 7) in the calculations (i.e., I
5, and I
accuracy, run at least 1mA quiescent bias current through
these resistors.
FIGURE 7. Limiter Bias Current vs Limiter Voltage.
L
–100
100
–25
–50
–75
–V
75
50
25
VH
0
0.0
S
+ 0.7V, V
L
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
+50 A out of pin 8). For good limiter voltage
®
0.5
–V
OPA689
1.0
S
+ 2.1V or V
H
H
1.5
– V
+V
S
H
Limiter Headroom (V)
– default limit voltages) = head-
or V
2.0
L
S
– 0.7V). They must also be at
Current = I
Limiter Headroom = +V
L
0.2V).
2.5
.
H
Maximum Over Temperature
Minimum Over Temperature
H
and V
H
VL
3.0
+V
and V
VH
S
or –I
L
3.5
–50 A out of pin
– 2.1V), you can
H
go to the Default
L
VL
(pin 8) and V
= V
(see Figure 1).
H
4.0
L
S
or V
– (–V
– V
H
4.5
H
or V
S
L
)
, the
5.0
L
L
.
14
When the limiter voltages need to be within 2.1V of the
supplies (V
impedance voltage sources to set V
errors due to bias current uncertainty. This will typically be
the case for single supply operation (V
runs 2.5mA through the resistive divider that sets V
V
limit voltages.
The limiters’ DC accuracy depends on attention to detail.
The two dominant error sources can be improved as follows:
• Power supplies, when used to drive resistive dividers that
• The resistor tolerances in the resistive divider can also
Other error sources also contribute, but should have little
impact on the limiters’ DC accuracy:
• Reduce offsets caused by the Limiter Input Bias Currents.
• Consider the signal path DC errors as contributing to the
• The Limiter Offset Voltage only slightly degrades the
Figure 8 shows how the limiters affect distortion perfor-
mance. Virtually no degradation in linearity is observed for
output voltages swinging right up to the limiter voltages.
FIGURE 8. Linearity Guardband.
L
set V
Using a more accurate source, or bypassing pins 5 and 8
with good capacitors, will improve limiter PSRR.
dominate. Use 1% resistors.
Select the resistors in the resistive divider(s) as described
above.
uncertainty in the useable output range.
limiter accuracy.
. This keeps errors due to I
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
H
0.9 1.0 1.1 1.2 1.3 1.4
and V
L
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
–V
L
, can contribute large errors (e.g., (5%).
S
+ 2.1V or V
± Limit Voltage (V)
VH
and I
HD2
HD3
H
1.5 1.6
H
VL
+V
and V
S
< 1% of the target
S
V
= +5V). Figure 2
1.7 1.8
O
– 2.1V), use low
R
f
= 0V
1
L
= 5MHz
L
= 500
DC
to minimize
±1Vp
1.9 2.0
H
and