AD9071 Analog Devices, AD9071 Datasheet - Page 8

• Manufacturer Part Number: AD9071
• Description: 10-Bit/ 100 MSPS A/D Converter
• Manufacturer: Analog Devices

AD9071
APPLICATION NOTES
THEORY OF OPERATION
The AD9071 employs a two-step subranging architecture with
digital error correction.
The sampling and conversion process is initiated by a rising edge
at the ENCODE input. The analog input signal is buffered by a
high speed differential amplifier and applied to a track-and-hold
(T/H) circuit, which captures the value of the input at the sam-
pling instant and maintains it for the duration of the conversion.
The coarse quantizer (ADC) produces a 5-bit estimate of the
input value. Its digital output is reconverted to analog form by
the reconstruction DAC and subtracted from the input signal in
the SUM AMP. The second stage quantizer generates a 6-bit
representation of the difference signal. The eleven bits are pre-
sented to the ENCODE LOGIC, which corrects for range over-
lap errors and produces an accurate 10-bit result.
Data are strobed to the output on the rising edge of the ENCODE
input, with the data from sample N appearing on the output
following ENCODE rising edge N+3.
USING THE AD9071
ENCODE Input
Any high-speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A track/hold
circuit is essentially a mixer, and any noise, distortion, or timing
jitter on the clock will be combined with the desired signal at
the A/D output. For that reason, considerable care has been
taken in the design of the ENCODE input of the AD9071, and
the user is advised to give commensurate thought to the clock
source. The lowest jitter clock source is a crystal oscillator pro-
ducing a pure sine wave.
The ENCODE input is fully TTL/CMOS compatible.
Digital Outputs
The digital outputs are CMOS compatible for lower power
consumption. 200
the AD9071 and the receiving logic to reduce transients and
improve SNR.
Analog Input
The analog input has been optimized for differential signal
input.
If driven single-endedly, the AIN should be connected to a
clean reference and bypassed to ground. For best dynamic
performance, impedances at AIN and AIN should match.
Special care was taken in the design of the analog input section
of the AD9071 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is +1.988 V to
+3.012 V (1.024 V p-p centered at +2.5 V). Out-of-range
Figure 18. Differential Analog Input Configuration
50
T1 - 1T
T1A
series resistors are recommended between
0.1 F
0.1 F
100
100
V
REF
(+2.5V)
AIN
AIN
AD9071
–8–
comparators detect when the analog input signal is out of this
range, and set the OR output signal HIGH. The digital outputs
are locked at plus or minus full scale (3FF
ages that are out of range, but between 1 V and 5 V. Input volt-
ages outside of this range may result in invalid codes at the
ADC’s output.
When the analog input signal returns to the nominal range, the
out-of-range comparators return the ADC to its active mode
and the device recovers in the overvoltage recovery time.
Voltage Reference
A stable and accurate 2.5 V voltage reference (V
built into the AD9071 (VREF OUT). In normal operation, the
internal reference is used by strapping Pins 3 and 4 of the AD9071
together. The internal reference can provide 100 A of extra
drive current that may be used for other circuits.
Some applications may require greater accuracy, improved
temperature performance, or adjustment of the gain of the
AD9071, which cannot be obtained by using the internal refer-
ence. For these applications, an external 2.5 V reference can be
connected to VREF IN, which requires 5 A of drive current
(see Figure 20).
The input range can be adjusted by varying the reference volt-
age applied to the AD9071. No appreciable degradation in
performance occurs when the reference is adjusted 4%. The
full-scale range of the ADC tracks reference voltage changes
linearly.
Timing
The performance of the AD9071 is insensitive to the duty
cycle of the clock over a wide range of operating conditions
(see Figure 15).
The AD9071 provides latched data outputs, with three pipeline
delays. Data outputs are available one propagation delay (t
after the rising edge of the encode command (see Figure 1). The
length of the output data lines, and loads placed on them, should
be minimized to reduce transients within the AD9071; these
transients can detract from the converter’s dynamic performance.
Figure 19. Single-Ended Analog Input Configuration
1 F
Figure 20. Using the AD780 Voltage Reference
+5V
50
+V
GND
O/P SELECT
IN
AD780
25
0.1 F
NC
TRIM
V
0.1 F
OUT
NC = NO CONNECT
100
1M
100
0.1 F
V
25k
REF
+5V
(+2.5V)
AIN
AIN
H
or 200
AD9071
V
REF
CC
AD9071
H
IN
– 2.5 V) is
) for volt-
REV. B
PD
)