AD9772EB Analog Devices, AD9772EB Datasheet - Page 7

• Manufacturer Part Number: AD9772EB
• Description: 14-Bit/ 160 MSPS TxDAC+ with 2x Interpolation Filter
• Manufacturer: Analog Devices

REV. 0
Pin No.
1, 2, 19, 20
3
4–15
16
17
18
23, 24
21, 22, 47, 48
25
26
27, 28
29
30
31
32
33
34
35
36
37, 41, 44
38
39
40
42
43
45, 46
Name
DCOM
DB13
DB12–DB1
DB0
MOD0
MOD1
NC
DVDD
PLLLOCK
RESET
DIV1, DIV0
CLK+
CLK–
CLKCOM
CLKVDD
PLLCOM
PLLVDD
LPF
SLEEP
ACOM
REFLO
REFIO
FSADJ
IOUTB
IOUTA
AVDD
Description
Digital Common.
Most Significant Data Bit (MSB).
Data Bits 1–12.
Least Significant Data Bit (LSB).
Invokes digital high-pass filter response (i.e., “half-wave” digital mixing mode). Active High.
Invokes “zero-stuffing” mode. Active High. Note, “quarter-wave” digital mixing occurs with
MOD0 also set HIGH.
No Connect, Leave Open.
Digital Supply Voltage (+2.7 V to +3.6 V).
Phase Lock Loop Lock Signal when PLL clock multiplier is enabled. High indicates PLL is
locked to input clock. Provides 1 clock output when PLL clock multiplier is disabled. Maxi-
mum fanout is one (i.e., <10 pF).
Resets internal divider by bringing momentarily high when PLL is disabled to synchronize inter-
nal 1 clock to the input data and/or multiple AD9772 devices.
DIV1 along with DIV0 sets the PLL’s prescaler divide ratio (refer to Table III.)
Noniverting input to differential clock. Bias to midsupply (i.e., CLKVDD/2).
Inverting input to differential clock. Bias to midsupply (i.e., CLKVDD/2).
Clock Input Common.
Clock Input Supply Voltage (+2.7 V to +3.6 V).
Phase Lock Loop Common.
Phase Lock Loop (PLL) Supply Voltage (+2.7 V to +3.6 V). To disable PLL clock multiplier,
connect PLLVDD to PLLCOM.
PLL Loop Filter Node.
Power-Down Control Input. Active High. Connect to ACOM if not used.
Analog Common.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie
REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie
REFLO to ACOM). Requires 0.1 F capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Analog Supply Voltage (+2.7 V to +3.6 V).
(MSB) DB13
NC = NO CONNECT
DCOM
DCOM
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
PIN FUNCTION DESCRIPTIONS
10
11
12
1
2
3
4
5
6
7
8
9
48 47 46 45 44
13 14 15 16 17 18 19 20 21 22 23 24
PIN CONFIGURATION
PIN 1
IDENTIFIER
(Not to Scale)
TOP VIEW
AD9772
–7–
43 42 41 40
39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
SLEEP
LPF
PLLVDD
PLLCOM
CLKVDD
CLKCOM
CLK–
CLK+
DIV0
DIV1
RESET
PLLLOCK
AD9772