AD9822 Analog Devices, AD9822 Datasheet - Page 12

• Manufacturer Part Number: AD9822
• Description: Complete 14-Bit CCD/CIS Signal Processor
• Manufacturer: Analog Devices

AD9822
CIRCUIT OPERATION
Analog Inputs—CDS Mode
Figure 8 shows the analog input configuration for the CDS
mode of operation. Figure 9 shows the internal timing for the
sampling switches. The CCD reference level is sampled when
CDSCLK1 transitions from high to low, opening S1. The CCD
data level is sampled when CDSCLK2 transitions from high to
low, opening S2. S3 is then closed, generating a differential output
voltage representing the difference between the two sampled levels.
The input clamp is controlled by CDSCLK1. When CDSCLK1
is high, S4 closes and the internal bias voltage is connected to
the analog input. The bias voltage charges the external 0.1 F
input capacitor, level-shifting the CCD signal into the AD9822’s
input common-mode range. The time constant of the input
clamp is determined by the internal 5 k resistance and the
external 0.1 F input capacitance.
Figure 8. CDS-Mode Input Configuration (All Three Chan-
nels Are Identical)
External Input Coupling Capacitors
The recommended value for the input coupling capacitors is
0.1 F. While it is possible to use a smaller capacitor, this larger
value is chosen for several reasons:
1. Signal Attenuation. The input coupling capacitor creates a
(INTERNAL)
CDSCLK1
CDSCLK2
capacitive divider with a CMOS integrated circuit’s input
capacitance, attenuating the CCD signal level. C
large relative to the IC’s 10 pF input capacitance in order to
minimize this effect.
CCD SIGNAL
Figure 9. CDS-Mode Internal Switch Timing
Q3
1 F
S1, S4 CLOSED
+
0.1 F
S1, S4 OPEN
S2 OPEN
S3 OPEN
OFFSET
C
0.1 F
IN
VINR
S2 CLOSED
S4
S3 CLOSED
AD9822
5k
4V
3V
AVDD
S1, S4 CLOSED
1.7k
2.2k
6.9k
S1
S2
INPUT CLAMP LEVEL
IS SELECTED IN THE
CONFIGURATION
REGISTER
S3
2pF
2pF
S2 CLOSED
IN
S3 CLOSED
should be
CML
CML
–12–
2. Linearity. Some of the input capacitance of a CMOS IC is
3. Sampling Errors. The internal 2 pF sample capacitors have
Analog Inputs—SHA Mode
Figure 10 shows the analog input configuration for the SHA
mode of operation. Figure 11 shows the internal timing for the
sampling switches. The input signal is sampled when CDSCLK2
transitions from high to low, opening S1. The voltage on the
OFFSET pin is also sampled on the falling edge of CDSCLK2,
when S2 opens. S3 is then closed, generating a differential out-
put voltage representing the difference between the sampled
input voltage and the OFFSET voltage. The input clamp is
disabled during SHA mode operation.
(OR CONNECT TO GND)
OPTIONAL DC OFFSET
(INTERNAL)
junction capacitance, which varies nonlinearly with applied
voltage. If the input coupling capacitor is too small, then the
attenuation of the CCD signal will vary nonlinearly with signal
level. This will degrade the system linearity performance.
a “memory” of the previously sampled pixel. There is a
charge redistribution error between C
sample capacitors for larger pixel-to-pixel voltage swings. As
the value of C
voltage will increase. With a C
redistribution error will be less than 1 LSB for a full-scale
pixel-to-pixel voltage swing.
CDSCLK2
Figure 10. SHA-Mode Input Configuration (All Three
Channels Are Identical)
Figure 11. SHA-Mode Internal Switch Timing
Q3
INPUT SIGNAL
S1, S2 OPEN
S3 OPEN
IN
is reduced, the resulting error in the sampled
OFFSET
S1, S2 CLOSED
VINR
VING
VINB
S3 CLOSED
AD9822
IN
value of 0.1 F, the charge
S2
S1
IN
and the internal
S3
S1, S2 CLOSED
2pF
2pF
S3 CLOSED
REV. A
CML
RED
CML
GREEN
BLUE