AD9853 Analog Devices, AD9853 Datasheet - Page 23

• Manufacturer Part Number: AD9853
• Description: Programmable Digital OPSK/16-QAM Modulator
• Manufacturer: Analog Devices

These register widths have been chosen to accommodate the
highest values of R for each interpolator. When values of R are
chosen that are less than the maximum value, then data will
accumulate only in the lesser significant bits of the output regis-
ter. This is an important point to consider since only 13 bits of
28 are passed on from Interpolator #1 to Interpolator #2, and
only 10 bits of 25 are passed on from Interpolator #2 to the
I and Q modulator (see Figure 36). If only the most significant
bits were to be passed on, then low R values would result in
most (possibly all) of the bits being 0s because data would have
accumulated only in the less significant bits of the output regis-
ter. Obviously, it is necessary to have a mechanism that allows
one to select which group of bits to pass on to the next stage in
order to prevent the loss of data by truncation.
In the AD9853 this mechanism is handled by means of the
Interpolator #1 and #2 Scaling Registers (control bus addresses
14h and 15h). The scaling word written into each register selects
a group of bits at the output of the appropriate interpolator. In
the case of Interpolator #1 this is a 13-bit group, while in the
case of Interpolator #2 it is a 10-bit group. Inspection of the
scaling registers indicates that Interpolator #1 uses a 5-bit scaling
word while Interpolator #2 uses a 6-bit scaling word.
At first inspection it would seem as though there are 32 and 64
scaling steps for Interpolator #1 and #2, respectively. This is
not the case, however. The scaling word is actually decoded in a
nonlinear manner and there is considerable overlap; i.e., several
different register values may actually select the same group of
bits at the interpolator output. Table III lists the relationship
between the scaling word value and the highest bit of the inter-
polator output register which becomes the most significant bit
(MSB) of the group selected.
Scaling
Register
Value
(Decimal)
0
1
2
3–4
5
6
7–9
10–11
12–14
15–19
20–24
25–30
31
Selection of the proper scaling value is dependent on the selec-
tion of R for the interpolator. It is desirable to choose a scale
value that ensures that the MSB of the selected group of bits
coincides with the highest useful bit in the output register. To
accomplish this condition, use the following rule:
REV. C
Interpolator #1
Table III. Interpolator Scale Bit Selection
Highest Bit
Selected
from
Output
Register
12
15
16
18
19
20
21
22
23
24
25
26
27
Scaling
Register
Value
(Decimal)
0
1
2
3–4
5–6
7–10
11–14
15–21
22–30
31–44
45–62
63
Interpolator #2
20
21
22
23
Highest Bit
Selected
from
Output
Register
12
14
15
16
17
18
19
24
–23–
Scaling Rule: For a particular interpolator, choose a nominal
Scaling Register value that is ONE LESS than the interpolation
rate (R) for the same interpolator.
For example, if Interpolator #1 is set for an interpolation rate of
6, then choose a Scaling Register value of 5 for Interpolator #1.
It has already been mentioned that the required number of bits
at the output of the CIC filter is a function of R. It turns out
that for values of R that are a power of 2, the number of bits
required to handle the growth of the output register is an inte-
ger. This results in a processing gain of unity for the CIC filter.
For values of R that are not a power of 2, the required number
of output bits is not an integer. This results in a processing gain
that is not unity. Tables IV and V detail the relationship be-
tween the Scaling Register values and the processing gain for
Interpolator #1 and Interpolator #2. Note that certain Scale
Register values for a particular R yield a processing gain greater
than unity. Thus, it is possible that the nominal Scaling Register
values will result in a total CIC processing gain of > 1.
WARNING: It is of utmost importance the user make certain
that the total processing gain of the data path be 1.
That is, the product of the FIR gain, Interpolator #1 gain, and
Interpolator #2 gain must be 1. This is because total process-
ing gains of > 1 may result in an overflow condition within the
CIC filters, which puts the hardware in a nonrecoverable state
(short of resetting the device). The contents of Tables IV and V
offer the user some flexibility in the choice of processing gains
for a particular interpolation rate. For example, let us assume
that an overall interpolation rate of 25 is required. A value of
R = 5 for both interpolators satisfies this requirement, which
leads to a Scale Register value of 4 for each interpolator. Note,
however, that under these conditions the processing gain for the
CIC filters alone is 3.053 (1.953 1.563).
There are two ways in which we can handle this situation. The
first is to scale the coefficients of the FIR filter by 0.3275 (1/3.053),
which reduces the total processing gain to 1. The disadvantage
here is that the FIR coefficients are 10-bit signed integers and
scaling by 0.3275 may result in an unacceptable level of trunca-
tion caused by the finite resolution. The second method makes
use of Tables IV and V. We can choose the Alternate Scale
Value of 5 (instead of 4) for Interpolator #2. This results in a
processing gain of 1.525 (1.953 0.781). We can now scale the
FIR coefficients by a more modest value of 0.6557 (1/1.525)
and net an overall gain of unity through the three stages. Of
course, we could just as easily have chosen the Alternate Scale
Value for Interpolator #1 and modified the FIR coefficients
accordingly. Typically, the choice of interpolator scale values
that results in an overall gain closest to (but not less than) one is
selected. Then the FIR coefficients are scaled downward to
yield unity gain.
AD9853