AD9882 Analog Devices, AD9882 Datasheet - Page 22

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

AD9882
2-WIRE SERIAL REGISTER MAP
The AD9882 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed
to write and read the Control Registers through the 2-wire serial interface port.
Hex
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
NOTE
1
The AD9882 only updates the PLL divide ratio when the LSBs are written to Register 02H.
Read and Write
or Read Only
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7–0
7–0
7–4
7–6
5–3
7–3
7–0
7–0
7–0
7–0
7–0
7–0
7–1
7–1
7–1
7–0
7–3
2
1
Value
0110 1001
1101 ****
01** ****
**00 1***
1000 0***
0000 1000
0001 0100
0010 0000
1000 0000
1000 0000
1000 0000
1000 000*
1000 000*
1000 000*
0010 0000
0111 1***
**** *0**
**** **0*
Default
Table IX. Control Register Map
Register Name
Chip Revisions
PLL Div MSB
PLL Div LSB
VCO Range
Charge Pump
Phase Adjust
Clamp Placement
Clamp Duration
Hsync Output Pulsewidth
Red Gain
Green Gain
Blue Gain
Red Offset
Green Offset
Blue Offset
Sync Separator Threshold
Sync-On-Green Threshold
Active Interface Override
Active Interface Select
–22–
Function
An 8-bit register that represents the silicon
level. Revision 0 = 0000 0000
This register is for Bits [11:4] of the PLL
divider. Larger values mean the PLL operates
at a faster rate. This register should be loaded
first whenever a change is needed. (This will
give the PLL more time to lock.)
Bits [3:0] LSBs of the PLL divider word. Links
to PLL MSB to make a 12-bit register.
Selects VCO frequency range.
Varies the current that drives the PLL loop filter.
ADC clock phase adjustment. Larger values
mean more delay (1 LSB = T/32).
Places the clamp signal an integer number of
clock periods after the trailing edge of Hsync.
Number of clock periods that the clamp signal
is actively clamping.
Sets the number of pixel clocks that HSOUT
will remain active.
Controls the ADC input range (contrast) of the
red channel. Larger values give less contrast.
Controls the ADC input range (contrast) of the
green channel. Larger values give less contrast.
Controls the ADC input range (contrast) of the
blue channel. Larger values give less contrast.
Controls the dc offset (brightness) of the red
channel. Larger values decrease brightness.
Controls the dc offset (brightness) of the green
channel. Larger values decrease brightness.
Controls the dc offset (brightness) of the blue
channel. Larger values decrease brightness.
Sets how many pixel clocks to count before
toggling high or low. This should be set to
some number greater than the maximum
Hsync or equalization pulsewidth.
Sets the voltage level of the Sync-on-Green
slicer’s comparator.
0 = No override
1 = User overrides, interface set by 0FH, Bit 1
0 = Analog interface active
1 = Digital interface active
This interface is selected only if Register 0FH,
Bit 2 is set to 1, or if both interfaces are active.
1
1
REV. A