AD9910 Analog Devices, AD9910 Datasheet - Page 5

• Manufacturer Part Number: AD9910
• Description: 3.3V CMOS Direct Digital Synthesizer
• Manufacturer: Analog Devices

PRELIMINARY TECHNICAL DATA
Parameter
CMOS LOGIC INPUTS
CMOS LOGIC OUTPUTS (1 mA Load)
POWER CONSUMPTION
SYNCHRONIZATION FUNCTION
1
2
3
4
5
To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise per-
formance of the device.
Wake-up time refers to the recovery from analog power-down modes (see section on Power-Down Modes of Operation). The longest time required is for the reference
clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used.
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK fre-
quency is the same as the external reference clock frequency.
SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.
This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
Serial Control Bus
Parallel Data Bus
Latency
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Single Tone Mode
With RAM or Linear Sweep Enabled
Rapid Power-Down Mode
Full-Sleep Mode
Maximum SYNC Clock Rate
SYNC_CLK Alignment Resolution
Maximum Frequency
Minimum Clock Pulse Width Low
Minimum Clock Pulse Width High
Maximum Clock Rise/Fall Time
Minimum Data Setup Time
Minimum Data Hold Time
Maximum Data Valid Time
Wake-Up Time
Minimum Reset Pulse Width High
I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time
I/O UPDATE, PS0, PS1 to SYNCCLK Hold Time
Maximum Frequency
Data setup time (to PDCLK)
Data hold time (to PDCLK)
I/O UPDATE to Frequency Change Prop Delay
I/O UPDATE to Phase Offset Change Prop Delay
I/O UPDATE to Amplitude Change Prop Delay
2
4
5
Rev. PrD| Page 5 of 13
Min
2.2
2.8
TBD
Typ
25
7
8
2
3
0
25
1
5
4
1
250
TBD
TBD
TBD
3
2
700
800
500
50
250
±1
TBD
TBD
Max
0.8
12
12
0.4
TBD
TBD
TBD
TBD
Unit
Mbps
ns
ns
ns
ns
ns
ns
ms
SYSCLK Cycles
ns
ns
Mword/sec
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
V
V
µA
µA
pF
V
V
mW
mW
mW
mW
MHz
SYSCLK Cycles
nsec
nsec
3
AD9910