AD9943 Analog Devices, AD9943 Datasheet - Page 17

• Manufacturer Part Number: AD9943
• Description: Complete 10-Bit and 12-Bit/ 25 MHz CCD Signal Processors
• Manufacturer: Analog Devices

CCD MODE TIMING
OUTPUT
SIGNAL
CLPOB
DATACLK
PBLK
DATA
OUTPUT
CCD
SIGNAL
DATA
CCD
SHD
SHP
NOTES
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
EFFECTIVE PIXELS
EFFECTIVE PIXEL DATA
t
ID
t
S1
N – 10
t
OD
N
t
ID
N – 9
OPTICAL BLACK PIXELS
t
S2
N + 1
Figure 15. Typical CCD Mode Line Clamp Timing
OB PIXEL DATA
Figure 14. CCD Mode Timing
Rev. B | Page 17 of 20
N – 8
t
CP
N + 2
HORIZONTAL
BLANKING
DUMMY PIXELS
N – 1
DUMMY BLACK
N + 9
AD9943/AD9944
EFFECTIVE PIXELS
EFFECTIVE DATA
N
N + 10