AD9116-EBZ Analog Devices, AD9116-EBZ Datasheet - Page 34

• Manufacturer Part Number: AD9116-EBZ
• Description: Dual, 8-/10-/12-/14-bit Low Power Digital-to-analog Converters
• Manufacturer: Analog Devices

AD9114/AD9115/AD9116/AD9117
SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 14.
Register
SPI Control
Power Down
Data Control
I DAC Gain
IRSET
Address
0x00
0x01
0x02
0x03
0x04
Bit
6
5
4
7
6
5
4
3
2
1
0
7
5
4
3
2
1
0
5:0
7
5:0
LSBFIRST
RESET
LNGINS
LDOSTAT
PWRDN
Q DACOFF
QCLKOFF
EXTREF
TWOS
IRISING
SIMULBIT
DCI_EN
DCOSGL
DCODBL
IRSETEN
Name
LDOOFF
I DACOFF
ICLKOFF
IFIRST
I DACGAIN[5:0]
IRSET[5:0]
0: The SPI instruction word utilizes a 5-bit address
1: Powers down all analog and digital circuitry except for SPI logic
0: Q data latched on DCLKIO rising edge
0: Allows simultaneous input and output enable on DCLKIO
1: Enables the on-chip R
Function
0: MSB first per SPI standard
1: LSB first per SPI standard
Note that the user must always change the LSB/MSB order in single-byte instructions
to avoid erratic behavior due to bit order errors
Execute software reset of SPI and controllers, reload default register values except
Register 0x00
1: Set software reset; write 0 on the next (or any following) cycle to release the reset
1: The SPI instruction word utilizes a 13-bit address
1: Turn core LDO voltage regulator off
0: Indicates core LDO voltage regulator is off
1: Indicates core LDO voltage regulator is on
1: Turns off Q DAC output current
1: Turns off I DAC output current
1: Turns off Q DAC clock
1: Turns off I DAC clock
1: Powers down internal voltage reference (external reference required)
0: Unsigned binary input data format
1: Twos complement input data format
0: Pairing of data—Q first of pair on data input pads
1: Pairing of data—I first of pair on data input pads (default)
1: I data latched on DCLKIO falling edge (default)
1: Disallows simultaneous input and output enable on DCLKIO
Controls the use of DCLKIO pad for data clock input
0: Data clock input disabled
1: Data clock input enabled (default)
Controls the use of DCLKIO pad for data clock output
0: Data clock output disabled
1: Data clock output enabled; regular strength driver
Controls the use of DCLKIO pad for data clock output
0: DCOBL data clock output disabled
1: DCOBL data clock output enabled; paralleled with DCOSGL for 2× drive current
DAC I fine gain adjustment; alters the full-scale current as shown in Figure 85
Changes the value of the on-chip R
DAC in ~0.25 dB steps (nonlinear); see Figure 84
000000: R
100000: R
111111: R
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SET
SET
SET
= 5 kΩ
= 1.5 kΩ
= 8.5 kΩ
SET
value to be changed
SET
resistor; this scales the full-scale current of the